 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 1 of 154 1 - 888 - 824 - 4184 ia 186es/ia188es 8 - bit/16 - bit microcontrollers data sheet ? ?
ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 2 of 154 1 - 888 - 824 - 4184 copyright 2011 by innovasic semiconductor, inc. published by innovasic semiconductor, inc. 3737 princeton drive ne, suite 130, albuquerque, nm 87107 amd, am186, and am188 are trademarks of advanced micro devices, inc . miles? is a trademark of innovasic semiconductor, inc. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 3 of 154 1 - 888 - 824 - 4184 table of contents list of figures ................................ ................................ ................................ ................................ .. 9 list of tables ................................ ................................ ................................ ................................ . 10 conventions ................................ ................................ ................................ ................................ ... 13 acronyms and abbreviations ................................ ................................ ................................ ........ 14 1. introduction ................................ ................................ ................................ ........................... 15 1.1 general description ................................ ................................ ................................ ..... 15 1.2 features ................................ ................................ ................................ ....................... 15 2. packaging, pin descriptions, and physical dimensions ................................ ....................... 16 2.1 packages and pinouts ................................ ................................ ................................ .. 16 2.1.1 ia186es tqfp package ................................ ................................ ................ 17 2.1.2 ia188es tqfp package ................................ ................................ ................ 20 2.1.3 tqfp physical dimensions ................................ ................................ ............ 23 2.1.4 ia186es pqfp package ................................ ................................ ................. 24 2.1.5 ia188es pqfp package ................................ ................................ ................. 27 2.1.6 pqfp physi cal dimensions ................................ ................................ ............ 30 2.2 pin descriptions ................................ ................................ ................................ .......... 31 2.2.1 a19/pio9, a18/pio8, a17/pio7, a16 C a0 address bus (synchronous outputs with trist ate) ................................ ................................ ....................... 31 2.2.2 ad15 C ad8 ( ia186es) address/data bus (level - sensitive synchronous inouts with tristate) ................................ ................................ .... 31 2.2.3 ao15 C ao8 ( ia188es) address bus (level - sensitive synchronous outputs with tristate) ................................ ................................ ....................... 31 2.2.4 ad7 C ad0 address/data bus (level - sensitive synchronous inouts with tristate) ................................ ................................ ................................ ............ 31 2.2.5 ale address latch enable (synchronous output) ................................ ......... 32 2.2.6 ardy asynchronous ready (level - sensitive asynchronous input) ................ 32 2.2.7 bhe_n/aden_n ( ia186es only) bus high enable (synchronous output with tristate)/address enable (input with internal pullup) .................. 32 2.2.8 clkouta clock output a (synchron ous output) ................................ ............ 33 2.2.9 clkoutb clock output b (synchronous output) ................................ ............ 33 2.2.10 cts0_n/enrx0_n/pio21 clear - to - send 0/enable - receive - r equest 0 (both are asynchronous inputs) ................................ ................................ ....... 33 2.2.11 den_n/ds_n/pio5 data enable /data strobe (both are synchronous outputs with tristate) ................................ ................................ ....................... 34 2.2.12 drq0/int5/pio12 dma request 0 (synchronous level - sensitive input)/maskable interrupt request 5 (asynchronous edge - triggered input) ................................ ................................ ................................ ............... 34 2.2.13 drq1/int6/pio13 dma request 1 (sy nchronous level - sensitive input)/maskable interrupt request 6 (asynchronous edge - triggered input) ................................ ................................ ................................ ............... 34 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 4 of 154 1 - 888 - 824 - 4184 2.2.14 dt/r_n/pio4 data transmit or receive (synchronous output with tristate) ................................ ................................ ................................ ............ 34 2.2.15 gnd ground ................................ ................................ ................................ .. 35 2.2.16 hlda bus hold acknowledge (synchronous output) ................................ .... 35 2.2.17 int0 maskable interrupt request 0 (asynchronous input) ............................ 35 2.2.18 int1/select_n maskable interrupt request 1/slave select (both are asynchronous inputs) ................................ ................................ ...................... 35 2.2.19 int2/inta0_n/pwd/pio31 maskable interrupt request 2 (asynchronous input)/interrupt acknowledge 0 (synchronous output)/ p ulse width demodulator (schmitt trigger input) ............................. 36 2.2.20 int3/inta1_n/irq maskable interrupt request 3 (asynchronous input)/interrupt acknowledge 1 (synchronous output)/ i nterrupt a cknowledge (synchronous output) ................................ ............................... 36 2.2. 21 int4/pio30 maskable interrupt request 4 (asynchronous input) .................. 37 2.2.22 lcs_n/once0_n lower memory chip select (synchronous output with internal pullup)/once mode request (input) ................................ ....... 37 2.2.23 mcs0_n/pio14 midrange memory chip select (synchronous output with internal pullup) ................................ ................................ ....................... 37 2.2.24 mcs2_n C mcs1_n (pio24 C pio 15) midrang e memory chip selects (synchronous outputs with internal pullup) ................................ .................... 37 2.2.25 mcs3_n/rfsh_n/pio25 midrange memory chip select (synchronous outputs with internal pullup)/automatic refresh (synchro nous output) ........ 38 2.2.26 nmi nonmaskable interrupt (synchronous edge - sensitive input) ................ 38 2.2.27 pcs1_n C pcs0_n (pio17 C pio16) periph eral chip selects 1 C 0 (synchronous outputs) ................................ ................................ ..................... 38 2.2.28 pcs2_n/cts1_n/enrx1_n/pio18 peripheral chip select 2 (synchronous output)/clear - to - send 1 (asynchronous input)/enable - receiver - request 1 ( asynchronous input) ................................ ...................... 39 2.2.29 pcs3_n/rts1_n/rtr1_n/pio18 peripheral chip select 3 (synchronous output)/ready - to - send 1 (asynchronous output)/ready - to - receive 1 (asynchronous input) ................................ ................................ ...................... 39 2.2.30 pcs5_n/a1/pio3 peripheral chip select 5 (synchronous output)/latched address bit [1] (synchronous output) ................................ .. 40 2.2.31 pcs6_n/a2/pio 2 peripheral chip select 6 (synchronous output)/latched address bit [2] (synchronous output) ................................ .. 40 2.2.32 pio31 C pio0 programmable i/o pins (asynchronous input/output open - drain) ................................ ................................ ................................ ...... 40 2.2.33 rd_n read strobe (synchronous output with tristate) ................................ ... 40 2.2.34 res_n reset (asynchronous level - sensitive input) ................................ ........ 40 2.2.35 rfsh2_n/aden_n ( ia188es only) refresh 2 (synchronous output with tristate)/address enable (input with internal pullup) ............................. 41 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 5 of 154 1 - 888 - 824 - 4184 2.2.36 rts0_n/rtr0_n /pio20 ready - to - send 0 (asynchronous output)/ready - to - receive 0 (asynchronous input) ................................ ................................ . 41 2.2.37 rxd0_n/pio23 receive data 0 (asynchronous input) ................................ ... 41 2.2.38 rxd1_n/pio28 receive data 1 (asynchronous input) ................................ ... 41 2.2.39 s2_n C s0_n bus cycle status (synchronous outputs with tristate) ............... 41 2.2.40 s6/lock_n/clkdiv2_n/pio29 bus cycle status bit [6] (synchronous output)/bus lock (synchronous output)/clock divide by 2 (input with internal pullup) ................................ ................................ ................................ 42 2.2.41 srd y/pio6 synchronous ready (synchronous level - sensitive input) ............ 42 2.2.42 tmrin0/pio11 timer input 0 (synchronous edge - sensitive input) ................ 42 2.2.43 tmrin1/pio0 timer input 1 (synchronous edge - sensitive input) .................. 43 2.2.44 tmrout0/pio10 timer output 0 (synchronous output) ................................ . 43 2.2.45 tmrout1/pio1 timer output 1 (synchronous output) ................................ ... 43 2.2.46 txd0/pio22 transmit data 0 (asynchronous output) ................................ .... 43 2.2.47 txd1/pio27 transmit data 1 (asynchronous output) ................................ .... 43 2.2.48 ucs_n/once1_n upper memory chip select (synchronous output)/once mode request 1 (input with internal pullup) ......................... 43 2.2.49 uzi_n/pio26 upper zero indicate (synchronous output) .............................. 44 2.2.50 v cc power supply (input) ................................ ................................ .............. 44 2.2.51 whb_n ( ia186es only ) write high byte (synchronous output with tristate) ................................ ................................ ................................ ............ 44 2.2.52 wlb_n/wb_n write low byte ( ia186es only ) (synchronous output with tristate)/write byte ( ia188es only ) (synchronous output with tristate) ................................ ................................ ................................ ............ 44 2.2.53 wr_n write strobe (synchronous output) ................................ .................... 44 2.2.54 x1 crystal inp ut ................................ ................................ ........................... 44 2.2.55 x2 crystal input ................................ ................................ ........................... 44 2.3 pins used by emulators ................................ ................................ .............................. 45 3 . maximum ratings, thermal characteristics, and dc parameters ................................ ....... 45 4. device architecture ................................ ................................ ................................ .............. 47 4.1 bus interface and control ................................ ................................ ........................... 47 4.2 clock and power management ................................ ................................ ................... 49 4.3 system clocks ................................ ................................ ................................ ............. 49 4.4 power - sav e mode ................................ ................................ ................................ ....... 50 4.5 initialization and reset ................................ ................................ ................................ 50 4.6 reset configuration register ................................ ................................ ...................... 50 4.7 chip selects ................................ ................................ ................................ ................. 50 4.8 chip - select timing ................................ ................................ ................................ ..... 50 4.9 ready - and wait - state programming ................................ ................................ .......... 51 4.10 chip - select overlap ................................ ................................ ................................ .... 51 4.11 upper - memory chip select ................................ ................................ ........................ 52 4.12 low - memory chip select ................................ ................................ ........................... 52 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 6 of 154 1 - 888 - 824 - 4184 4.13 midrange - memory chip selects ................................ ................................ ................. 52 4.14 peripheral chip selects ................................ ................................ ............................... 53 4.15 refresh control ................................ ................................ ................................ ........... 53 4.16 interrupt control ................................ ................................ ................................ .......... 53 4.17 interrupt types ................................ ................................ ................................ ............ 54 4.18 timer control ................................ ................................ ................................ .............. 55 4.19 watchdog timer ................................ ................................ ................................ .......... 56 4.20 direct memory access ................................ ................................ ................................ 57 4.21 dma operation ................................ ................................ ................................ ........... 57 4.22 dma channel control registers ................................ ................................ ................ 58 4.23 dma priority ................................ ................................ ................................ .............. 59 4.24 pulse width demodulation ................................ ................................ ......................... 59 4.25 asynchronous serial ports ................................ ................................ .......................... 60 4.26 programmable i/o ................................ ................................ ................................ ....... 60 5. peripheral architecture ................................ ................................ ................................ ......... 62 5.1 control and registers ................................ ................................ ................................ .. 62 5.1.1 relreg (0feh) ................................ ................................ .............................. 64 5.1.2 rescon (0f6h) ................................ ................................ .............................. 64 5.1.3 prl (0f4h) ................................ ................................ ................................ ...... 64 5.1.4 auxcon (0f2h) ................................ ................................ ............................ 65 5.1.5 syscon (0f0h) ................................ ................................ .............................. 66 5.1.6 wdtcon (0e6h) ................................ ................................ ........................... 67 5.1.7 edram (0e4h) ................................ ................................ .............................. 68 5.1.8 cdram (0e2h) ................................ ................................ .............................. 69 5.1.9 mdram (0e0h) ................................ ................................ ............................. 69 5.1.10 d1con (0dah) and d0con (0cah) ................................ ............................... 69 5.1.11 d1tc (0d8h) and d0tc (0c8h) ................................ ................................ ..... 71 5.1.12 d1dsth (0d6h) and d0dsth (0c6h) ................................ ........................... 72 5.1.13 didstl (0d4h) and d0dstl (0c4h) ................................ ............................ 72 5.1.14 d1srch (0d2h) and d0srch (0c2h) ................................ ........................... 72 5.1.15 d1srcl (0d0h) and d0srcl (0c0h) ................................ ............................ 73 5.1.16 mpcs (0a8h) ................................ ................................ ................................ .. 73 5.1.17 mmcs (0a6h) ................................ ................................ ................................ . 75 5.1.18 pacs (0a4h) ................................ ................................ ................................ ... 76 5.1.19 lmcs (0a2h) ................................ ................................ ................................ .. 77 5.1.20 umcs (0a0h) ................................ ................................ ................................ .. 79 5.1.21 sp0baud (088h) ................................ ................................ ........................... 80 5.1.22 sp1baud (018h) ................................ ................................ ........................... 80 5.1.23 sp0rd (086h) and sp1rd ( 016h) ................................ ................................ . 81 5.1.24 sp0td (084h) and sp1td (014h) ................................ ................................ .. 82 5.1.25 sp0sts (082h) and sp1sts (012h) ................................ ............................... 82 5.1.26 sp0ct (080h) and sp1ct (010h) ................................ ................................ .. 84 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 7 of 154 1 - 888 - 824 - 4184 5.1.27 pdata1 (07ah) and pdata0 (074h) ................................ ........................... 87 5.1.28 pdir1 (078h) and pdir0 (072h) ................................ ................................ ... 89 5.1.29 pmode1 (076h) and pmode0 (070h) ................................ ......................... 90 5.1.30 t1con (05eh) and t0con (056h) ................................ ................................ 91 5.1.31 t2con (066h) ................................ ................................ ................................ 92 5.1.32 t2compa (062h), t1compb (05ch), t1compa (05ah), t0compb (054h), and t0compa (052h) ................................ ................... 93 5.1.33 t2cnt (060h), t1cnt (058h), and t0cnt (050h) ................................ ..... 93 5.1.34 sp0con (044h) and sp1con (042h) (master mode) ................................ .. 94 5.1.35 i4con (040h) (master mode) ................................ ................................ ........ 95 5.1.36 i3con (03eh) and i2con (03ch) (master mode) ................................ ......... 95 5.1.37 i1con (03ah) and i0c on (038h) (master mode) ................................ ......... 96 5.1.38 tcucon (032h) (master mode) ................................ ................................ ... 97 5.1.39 t2intcon (03ah), t1intcon (038h), and t0intcon (032h) (s lave mode) ................................ ................................ ................................ .. 97 5.1.40 dma1con/int6con (036h) and dma0con/int5con (034h) (master mode) ................................ ................................ ................................ 98 5.1.41 dma1con/int6 (036h) and dma0con/i nt5 (034h) (slave mode) ................................ ................................ ................................ .............. 98 5.1.42 intsts (030h) (master mode) ................................ ................................ ...... 99 5.1.43 intsts (030h) (slave mode) ................................ ................................ ........ 99 5.1.44 reqst (02eh) (master mode) ................................ ................................ ..... 100 5.1.45 reqst (02eh) (slave mode) ................................ ................................ ....... 101 5.1.46 inserv ( 02ch) (master mode) ................................ ................................ ... 101 5.1.47 inserv (02ch) (slave mode) ................................ ................................ ...... 102 5.1.48 primsk (02ah) (master and slave mode) ................................ .................. 10 3 5.1.49 imask (028h) (master mode) ................................ ................................ ..... 103 5.1.50 imask (028h) (slave mode) ................................ ................................ ....... 104 5.1.51 pollst (026h) (master mode) ................................ ................................ ... 105 5.1.52 poll (024h) (master mode) ................................ ................................ ........ 105 5.1.53 eoi (022h) e nd - o f - i nterrupt register (master mode) ................................ 106 5.1.54 eoi (022h) specific e nd - o f - i nterrupt register (slave mode) .................... 106 5.1.55 intvec (020h) int errupt vec tor register (slave mode) ............................ 107 5.2 reference documents ................................ ................................ ............................... 107 6. ac specifications ................................ ................................ ................................ ............... 108 7 . instruction set summary table ................................ ................................ .......................... 134 7.1 key to abbreviations used in instruction set summary table ................................ 144 7.1.1 operand address byt e ................................ ................................ .................. 144 7.1.2 modifier field ................................ ................................ ............................... 144 7.1.3 auxiliary field ................................ ................................ .............................. 144 7.1.4 r /m field ................................ ................................ ................................ ........ 145 7.1.5 displacement ................................ ................................ ................................ 145 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 8 of 154 1 - 888 - 824 - 4184 7.1.6 immediate bytes ................................ ................................ ........................... 145 7. 1.7 segment override prefix ................................ ................................ .............. 145 7.1.8 segment register ................................ ................................ .......................... 145 7.2 explanation of notation used in instruction set summary table ............................ 146 7.2.1 opcode ................................ ................................ ................................ .......... 146 7.2.2 flags affected after instruction ................................ ................................ ... 147 8. innovasic/amd part number cross - reference tables ................................ ...................... 148 9. errata ................................ ................................ ................................ ................................ ... 150 9.1 errata summary ................................ ................................ ................................ ......... 150 9.2 errata detail ................................ ................................ ................................ .............. 150 10. revision history ................................ ................................ ................................ ................. 153 11. for additional information ................................ ................................ ................................ . 154 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 9 of 154 1 - 888 - 824 - 4184 list of figures figure 1 . ia186es tqfp package diagram ................................ ................................ ................ 17 figure 2 . ia 188es tqfp package diagram ................................ ................................ ................ 20 figure 3 . tqfp package dimensions ................................ ................................ ........................... 23 figure 4 . ia186es pqfp package diagram ................................ ................................ ................ 24 figure 5 . ia188es pqfp package diagram ................................ ................................ ................ 27 figure 6 . pqfp package dimensions ................................ ................................ ........................... 30 figure 7 . functional block diagram ................................ ................................ ............................ 48 figure 8. crystal configuration ................................ ................................ ................................ .... 49 figure 9. organization of clock ................................ ................................ ................................ ... 49 figure 10. dma unit ................................ ................................ ................................ .................... 58 figure 11. typical waveform at the int2/int0_n/pwd pin ................................ ............................ 59 figure 12. read cycle ................................ ................................ ................................ ................. 113 figure 13. multiple read cycles ................................ ................................ ................................ 114 figure 14. write cycle ................................ ................................ ................................ ................ 116 figure 15. multiple write cycles ................................ ................................ ............................... 117 figure 16. psram read cycle ................................ ................................ ................................ .. 119 figure 17. psram write cyc le ................................ ................................ ................................ . 121 figure 18. psram refresh cycle ................................ ................................ .............................. 123 figure 19. interrupt acknowledge cycle ................................ ................................ .................... 124 figure 20. software halt cycle ................................ ................................ ................................ .. 126 figure 21. clock active mode ................................ ................................ ................................ . 128 figure 22. clock power - save mode ................................ ................................ ........................ 128 figure 23. srdy synchronous ready ................................ ................................ ........................ 129 figure 24. ardy asynchronous ready ................................ ................................ ...................... 130 figure 25. peripherals ................................ ................................ ................................ ................. 130 figure 26. reset 1 ................................ ................................ ................................ ....................... 131 figure 27. reset 2 ................................ ................................ ................................ ....................... 131 figure 28. bus hold entering ................................ ................................ ................................ ..... 132 figure 29. bus hold leaving ................................ ................................ ................................ ...... 132 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 10 of 154 1 - 888 - 824 - 4184 list of tables table 1 . ia186es tqfp numeric pin listing ................................ ................................ ............. 18 table 2 . ia186es tqfp alphabetic pin listing ................................ ................................ .......... 19 table 3 . ia188es tqfp numeric pin listing ................................ ................................ ............. 21 table 4 . ia188es tqfp alphabetic pin listing ................................ ................................ .......... 22 table 5 . ia186es pqfp numeric pin listing ................................ ................................ ............. 25 table 6 . ia186es pqfp alphabetic pin listing ................................ ................................ .......... 26 table 7 . ia188es pqfp numeric pin listing ................................ ................................ ............. 28 table 8 . ia188es pqfp alphabetic pin listing ................................ ................................ .......... 29 table 9 . bus cycle types for bhe_n and ad 0 ................................ ................................ ............... 32 table 10 . bus cycle types for s2_n, s1_n, and s0_n ................................ ................................ ... 42 table 11. ia186es and ia188es absolute maximum ratings ................................ ................... 45 table 12. ia186es and ia188es thermal characteristics ................................ .......................... 45 table 13. dc characteristics over commercial operating ranges ................................ ............. 46 table 14. interrupt types ................................ ................................ ................................ .............. 54 table 15. default status of pio pins at reset ................................ ................................ .............. 61 table 16. peripheral control registers ................................ ................................ ......................... 63 table 17. peripheral control block rel ocation reg ister ................................ .............................. 64 table 18. reset config uration reg ister ................................ ................................ ........................ 64 table 19. p rocessor r elease l evel register ................................ ................................ ................. 65 table 20. aux iliary con figuration register ................................ ................................ ................. 65 table 21. system con figuration register ................................ ................................ ..................... 66 table 22. w atchdog t imer con trol register ................................ ................................ ................ 67 table 23. e nable d ynamic ram refresh control register ................................ ......................... 68 table 24. c ount for dynamic ram refresh control register ................................ .................... 69 table 25. m emory partition for d ynamic ram refresh control register ................................ . 69 table 26. dma control registers ................................ ................................ ................................ 69 table 27. dma tr ansfer count registers ................................ ................................ .................... 71 table 28. d ma d e st ination address high register ................................ ................................ .... 72 table 29. d ma d e st ination address l ow register ................................ ................................ ..... 72 table 30. d ma s ou rc e address h igh register ................................ ................................ ............ 73 table 31. d ma s ou rc e address l ow register ................................ ................................ ............ 73 table 32. mcs and pcs auxiliar y register ................................ ................................ ................ 74 table 33. m idrange m emory c hip s elect register ................................ ................................ ...... 75 ta ble 34. p eripher a l c hip s elec t register ................................ ................................ .................... 76 table 35. low - memory chip select register ................................ ................................ .............. 78 table 36. u pper - m emor y c hip s elect re gister ................................ ................................ ........... 79 table 37. baud rates ................................ ................................ ................................ .................... 81 table 38. s erial p ort baud rate divisor registers ................................ ................................ ....... 81 table 39. s erial p ort r eceive registers ................................ ................................ ........................ 82 table 40. s erial p ort t ransmit registers ................................ ................................ ...................... 82 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 11 of 154 1 - 888 - 824 - 4184 table 41. s er ial p ort st atu s register ................................ ................................ ............................ 83 table 42. s erial p ort control registers ................................ ................................ ........................ 84 table 43. pio pin assignments ................................ ................................ ................................ .... 88 table 44. pdata 0 ................................ ................................ ................................ ...................... 89 table 45. pdata 1 ................................ ................................ ................................ ...................... 89 table 46. pio mode and pio direction sett ings ................................ ................................ ......... 89 table 47. pdir0 ................................ ................................ ................................ ........................... 90 table 48. pdir1 ................................ ................................ ................................ ........................... 9 0 table 49. pmode 0 ................................ ................................ ................................ ...................... 90 table 50. pmode1 ................................ ................................ ................................ ...................... 90 table 51. t ime r0 and t ime r1 mode and con trol registers ................................ ......................... 91 table 52. t ime r2 mode and con trol registers ................................ ................................ ............ 92 table 53. t ime r maxcount com pare registers ................................ ................................ ............ 93 table 54. t imer c ou nt registers ................................ ................................ ................................ .. 94 table 55. s erial p ort interrupt con trol registers ................................ ................................ ......... 94 table 56. i nt 4 con trol register ................................ ................................ ................................ .. 95 table 57. i nt 2 / i nt 3 con trol register ................................ ................................ ........................ 96 table 58. i nt 0 / i nt 1 con trol register ................................ ................................ ........................ 96 table 59. t imer c ontrol u nit interrupt con trol register ................................ ............................. 97 table 60. t imer int errupt con trol register ................................ ................................ .................. 97 table 61. dma an d int errupt con trol register (master mode) ................................ ................... 98 table 62. dma and int errupt con trol register (slave mode) ................................ ..................... 98 table 63. int errupt st atu s register (master mode) ................................ ................................ ...... 99 table 64. int errupt st atu s register (slave mode) ................................ ................................ ........ 99 table 65. interrupt req ue st register (ma ster mode) ................................ ................................ . 100 table 66. interrupt req ue st register (slave mode) ................................ ................................ ... 101 table 67. in - serv ice register (master mode) ................................ ................................ ............ 102 table 68. in - serv ice register (slave mode) ................................ ................................ ............... 102 table 69. pri ority m a sk register ................................ ................................ ................................ 103 table 70. i nterrupt mask register (master mode) ................................ ................................ .. 104 table 71. i nterrupt mask register (slave mode) ................................ ................................ ..... 104 table 72. poll st atus register ................................ ................................ ................................ . 105 table 73. poll register ................................ ................................ ................................ ................ 106 table 74. e nd - o f - i nterrupt register ................................ ................................ ........................... 106 table 75. specific e nd - o f - i nterrupt register ................................ ................................ ............. 106 table 76. int errupt vec tor register ................................ ................................ ............................ 107 table 77. alphabetic key to waveform parameters ................................ ................................ .. 108 table 78. numeric key to waveform parameters ................................ ................................ ...... 110 table 79. read cycle timing ................................ ................................ ................................ ..... 115 table 80. write cycle timing ................................ ................................ ................................ .... 118 table 81. psram read cycle timing ................................ ................................ ....................... 120 table 82. psram write cycle timing ................................ ................................ ...................... 122 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 12 of 154 1 - 888 - 824 - 4184 table 83. psram refresh cycle timing ................................ ................................ .................. 123 table 84. interrupt acknowledge c ycle timing ................................ ................................ ........ 125 table 85. software halt cycle timing ................................ ................................ ....................... 127 table 86. clock timing ................................ ................................ ................................ .............. 129 table 87. ready and peripheral timing ................................ ................................ ..................... 131 table 88. reset and bus hold timing ................................ ................................ ........................ 133 table 89. instruction set summary ................................ ................................ ............................ 134 table 90. innovasic/amd part number cross - reference for the tqfp ................................ ... 148 table 91. innovasic/amd part number cros s - reference for the pqfp ................................ ... 149 table 92. summary of errata ................................ ................................ ................................ ...... 150 table 93. revision history ................................ ................................ ................................ ......... 153 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 13 of 154 1 - 888 - 824 - 4184 conventions arial bold designates headings, figure captions, and table captions. blue designates hyperlinks (pdf copy only). italics designates emphasis or caution related to nearby information. italics is also used to de signate variables, refer to related documents, and to differentiate terms from other common words (e.g., during refresh cycles, the a and ad busses may not have the same address during the address phase of the ad bus cycle. ). ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 14 of 154 1 - 888 - 824 - 4184 acronyms and abbreviations amd advanced micro devices bic bus interface and control cdram c ount for dynamic ram csc chip selects and control da disable address dma direct memory access eoi end of interrupt inserv in - service isr interr upt service routine lmcs low - memory chip select mc maximum count mdram m emory partition for d ynamic ram miles ? managed ic lifetime extension system mmcs m idrange m emory c hip s elect nmi nonmaskable interrupt pcb peripheral control block pio programmable i/o pll phase - lock - loop por power - on reset pqfp plastic quad flat package psram pseudo - static ram rcu refresh control unit rohs restriction of hazardous substances sfnm special fully nested mode syscon system configuration register tqfp thin quad flat package uart universal asynchronous receiver - transmitter umcs upper memory chip select wdt watchdog timer ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 15 of 154 1 - 888 - 824 - 4184 1. introduction the ia186es/ia188es is a form, fit, and function replacement for the original advanced micro devices (amd ) am186es/188es family of microcontro llers. innovasic produces replacement ics using its miles ? , or managed ic lifetime extension system, cloning technology that produces replacement ics far more complex than emulation while ensuring they are compatible with the original ic. miles capture s the design of a clone so it can be produced even as silicon technology advances. miles also verifies the clone against the original ic so that even the undocumented features are duplicated. 1.1 general description the ia186es/ia188es family of microcontro llers replaces obsolete amd am186es/188es devices, allowing customers to retain existing board designs, software compilers/assemblers, and emu lation tools and thus avoid expensive redesign efforts. the ia186es/ia188es microcontrollers are an upgrade for th e 80c186/188 microcontroller designs, with integrated peripherals to provide increased functionality and reduce system costs. the innovasic devices are designed to satisfy requirements of embedded products designed for teleco mmunications, office automatio n/ storage, and industrial controls. 1.2 features pin - for - pin compatible with amd am186es/188es devices all features are retained, including: C a phase - lock loop ( pll ) allowing same crystal/system clock frequency C an 8086/8088 instruction set with additional 186 i nstruction set extensions C a programmable interrupt controller C two direct memory access ( dma ) channels C three 16 - bit timers C a wait - state generator and programmable chip select logic C a d edicated watch dog timer (wdt) C two independent asynchronous serial ports ( uarts) o dma capability o hardware flow control o 7 - , 8 - , or 9 - bit data capability C pulse width demodulator feature C up to 32 programmable i/o (pio) pins a pseudo - static/dynamic ram controller a fully static cmos design 40 - mhz operation at industrial operating con ditions +5 - vdc power supply ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 16 of 154 1 - 888 - 824 - 4184 2. packaging, pin descriptions, and physical dimensions information on the packages and pin descriptions for the ia186es and the ia188es is provided separately. refer to sections, figures, and tables for information on the device of interest. 2.1 packages and pinouts the innovasic semiconductor ia186es and ia188es microcontroller is available in the following packages: 10 0 - pin thin quad flat package ( tqfp ), equivalent to original sqfp package 100 - plastic quad flat package (pqfp), equiv alent to original pqfp package ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 17 of 154 1 - 888 - 824 - 4184 2.1.1 ia186es t qfp package the pinout for the ia186 es t qfp package is as shown in figure 1. the corresponding pinout is provided in table s 1 and 2 . figure 1 . ia186es tqfp package diagram ? i n t 4 / p i o 3 0 m c s 1 _ n / p i o 1 5 m c s 0 _ n / p i o 1 4 d e n _ n / d s _ n / p i o 5 d t / r _ n / p i o 4 n m i s r d y / p i o 6 h o l d h l d a w l b _ n w h b _ n g n d a 0 a 1 v c c a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 1 d r q 0 / i n t 5 / p i o 1 2 d r q 1 / i n t 6 / p i o 1 3 t m r i n 0 / p i o 1 1 t m r o u t 0 / p i o 1 0 t m r o u t 1 / p i o 1 t m r i n 1 / p i o 0 r e s _ n g n d m c s 3 _ n / r f s h _ n / p i o 2 5 m c s 2 _ n / p i o 2 4 v c c p c s 0 _ n / p i o 1 6 p c s 1 _ n / p i o 1 7 g n d p c s 2 _ n / c t s 1 _ n / e n r x 1 _ n / p i o 1 8 p c s 3 _ n / r t s 1 _ n / r t r 1 _ n / p i o 1 9 v c c p c s 5 _ n / a 1 / p i o 3 p c s 6 _ n / a 2 / p i o 2 l c s _ n / o n c e 0 _ n u c s _ n / o n c e 1 _ n i n t 0 i n t 1 / s e l e c t _ n i n t 2 / i n t a 0 _ n / p w d / p i o 3 1 i n t 3 / i n t a 1 _ n / i r q a d 0 a d 8 a d 1 a d 9 a d 2 a d 1 0 a d 3 a d 1 1 a d 4 a d 1 2 a d 5 g n d a d 1 3 a d 6 v c c a d 1 4 a d 7 a d 1 5 s 6 / l o c k _ n / c l k d i v 2 _ n / p i o 2 9 u z i _ n / p i o 2 6 t x d 1 / p i o 2 7 r x d 1 / p i o 2 8 c t s 0 _ n / e n r x 0 _ n / p i o 2 1 r x d 0 / p i o 2 3 t x d 0 / p i o 2 2 r t s 0 _ n / r t r 0 _ n / p i o 2 0 b h e _ n / a d e n _ n w r _ n r d _ n a l e a r d y s 2 _ n s 1 _ n s 0 _ n g n d x 1 x 2 v c c c l k o u t a c l k o u t b g n d a 1 9 / p i o 9 a 1 8 / p i o 8 v c c a 1 7 / p i o 7 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 i a 1 8 6 e s t q f p ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 18 of 154 1 - 888 - 824 - 4184 table 1 . ia186es tqfp numeric pin listing pin name pin name pin name 1 ad0 35 gnd 68 hold 2 ad8 36 x1 69 srdy/pio6 3 ad1 37 x2 70 nmi 4 ad9 38 v cc 71 dt/r_n/pio4 5 ad2 39 clkouta 72 den_n/ds_n/pi o5 6 ad10 40 clkoutb 73 mcs0_n/pio14 7 ad3 41 gnd 74 mcs1_n/pio15 8 ad11 42 a19/pio9 75 int4/pio30 9 ad4 43 a18/pio8 76 int3/inta1_n/irq 10 ad12 44 v cc 77 int2/inta0_n/pwd/pio31 11 ad5 45 a17/pio7 78 int1/select_n 12 gnd 46 a16 79 int0 13 ad13 47 a15 80 ucs_n/once1_n 14 ad6 48 a14 81 lcs_n/once0_n 15 v cc 49 a13 82 pcs6_n/a2/pio2 16 ad14 50 a12 83 pcs5_n/a1/pio3 17 ad7 51 a11 84 v cc 18 ad15 52 a10 85 pcs3_n/rts1_n/rtr1_n/pio19 19 s6/lock_n/clkdiv2 _n /pio29 53 a9 86 pc s2_n/cts1_n/enrx1_n/pio18 20 uzi_n/pio26 54 a8 87 gnd 21 txd1/pio27 55 a7 88 pcs1_n/pio17 22 rxd1/pio28 56 a6 89 pcs0_n/pio16 23 cts0_n/enrx0_n/pio21 57 a5 90 v cc 24 rxd0/pio23 58 a4 91 mcs2_n/pio24 25 txd0/pio22 59 a3 92 mcs3_n/rfsh_n/pi o25 26 rts0_n/rtr0_n/pio20 60 a2 93 gnd 27 bhe_n/aden_n 61 v cc 94 res_n 28 wr_n 62 a1 95 tmrin1/pio0 29 rd_n 63 a0 96 tmrout1/pio1 30 ale 64 gnd 97 tmrout0/pio10 31 ardy 65 whb_n 98 tmrin0/pio11 32 s2_n 66 wlb_n 99 drq1/int6/pio13 33 s1_n 67 hlda 100 drq0/int5/pio12 34 s0_n ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 19 of 154 1 - 888 - 824 - 4184 table 2 . ia186es tqfp alphabetic pin listing name pin name pin name pin a0 63 ad14 16 pcs2_n/cts1_n/enrx1_n/pio18 86 a1 62 ad15 18 pcs3_n/rts1_n/rtr1_n/pio19 85 a2 60 ale 30 pcs5_n/a1/pio3 83 a3 59 ardy 30 pcs6_n/a2/pio2 82 a4 58 bhe_n/aden_n 27 rd_n 29 a5 57 clkouta 39 res_n 94 a6 56 clkoutb 40 rts0_n/rtr0_n/pio20 26 a7 55 cts0_n/enrx0_n/pio21 23 rxd0/pio23 24 a8 54 den_n/ds_n/pio5 72 rxd1/pio 28 22 a9 53 drq0/int5/pio12 100 s0_n 34 a10 52 drq1/int6/pio13 99 s1_n 33 a11 51 dt/r_n/pio4 71 s2_n 32 a12 50 gnd 12 s6/lock_n/clkdiv2 _n /pio29 19 a13 49 gnd 36 srdy/pio6 69 a14 48 gnd 41 tmrin0/pio11 98 a15 47 gnd 64 tmrin1/pio0 9 5 a16 46 gnd 87 tmrout0/pio10 97 a17/pio7 45 gnd 93 tmrout1/pio1 96 a18/pio8 43 hlda 67 txd0/pio22 25 a19/pio9 42 hold 68 txd1/pio27 21 ad0 1 int0 79 ucs_n/once1_n 80 ad1 3 int1/select_n 78 uzi_n/pio26 20 ad2 5 int2/inta0_n/pwd/pio3 1 77 v cc 15 ad3 7 int3/inta1_n/irq 76 v cc 38 ad4 9 int4/pio30 75 v cc 44 ad5 11 lcs_n/once0_n 81 v cc 61 ad6 14 mcs0_n/pio14 73 v cc 84 ad7 17 mcs1_n/pio15 74 v cc 90 ad8 2 mcs2_n/pio24 91 whb_n 65 ad9 4 mcs3_n/rfsh_n/pio25 92 wlb_n 66 ad10 6 nmi 70 wr_n 28 ad11 8 pcs0_n/pio16 89 x1 36 ad12 10 pcs1_npio 88 x2 37 ad13 13 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 20 of 154 1 - 888 - 824 - 4184 2.1.2 ia188es t qfp package the pinout for the ia186es t qfp package is as shown in figure 2. the corresponding pinout is provided in tables 3 and 4. figure 2 . ia188es tqfp package diagram ? i n t 4 / p i o 3 0 m c s 1 _ n / p i o 1 5 m c s 0 _ n / p i o 1 4 d e n _ n / d s _ n / p i o 5 d t / r _ n / p i o 4 n m i s r d y / p i o 6 h o l d h l d a w b _ n g n d g n d a 0 a 1 v c c a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 1 d r q 0 / i n t 5 / p i o 1 2 d r q 1 / i n t 6 / p i o 1 3 t m r i n 0 / p i o 1 1 t m r o u t 0 / p i o 1 0 t m r o u t 1 / p i o 1 t m r i n 1 / p i o 0 r e s _ n g n d m c s 3 _ n / r f s h _ n / p i o 2 5 m c s 2 _ n / p i o 2 4 v c c p c s 0 _ n / p i o 1 6 p c s 1 _ n / p i o 1 7 g n d p c s 2 _ n / c t s 1 _ n / e n r x 1 _ n / p i o 1 8 p c s 3 _ n / r t s 1 _ n / r t r 1 _ n / p i o 1 9 v c c p c s 5 _ n / a 1 / p i o 3 p c s 6 _ n / a 2 / p i o 2 l c s _ n / o n c e 0 _ n u c s _ n / o n c e 1 _ n i n t 0 i n t 1 / s e l e c t _ n i n t 2 / i n t a 0 _ n / p w d / p i o 3 1 i n t 3 / i n t a 1 _ n / i r q a d 0 a o 8 a d 1 a o 9 a d 2 a o 1 0 a d 3 a o 1 1 a d 4 a o 1 2 a d 5 g n d a o 1 3 a d 6 v c c a o 1 4 a d 7 a o 1 5 s 6 / l o c k _ n / c l k d i v 2 _ n / p i o 2 9 u z i _ n / p i o 2 6 t x d 1 / p i o 2 7 r x d 1 / p i o 2 8 c t s 0 _ n / e n r x 0 _ n / p i o 2 1 r x d 0 / p i o 2 3 t x d 0 / p i o 2 2 r t s 0 _ n / r t r 0 _ n / p i o 2 0 r f s h 2 _ n / a d e n _ n w r _ n r d _ n a l e a r d y s 2 _ n s 1 _ n s 0 _ n g n d x 1 x 2 v c c c l k o u t a c l k o u t b g n d a 1 9 / p i o 9 a 1 8 / p i o 8 v c c a 1 7 / p i o 7 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 i a 1 8 8 e s t q f p ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 21 of 154 1 - 888 - 824 - 4184 table 3 . ia188es tqfp numeric pin listing pin name pin name pin name 1 ad0 35 gnd 68 hold 2 ao8 36 x1 69 srdy/pio6 3 ad1 37 x2 70 nmi 4 ao9 38 v cc 71 dt/r_n/pio4 5 ad2 39 clkouta 72 den_n/ds_n/pio5 6 ao10 40 clkoutb 73 mcs0_n/pio14 7 ad3 41 gnd 74 mcs1_n/pio15 8 ao11 42 a19/pio9 75 int4/pio30 9 ad4 43 a18/pio8 76 int3/inta1_n/irq 10 ao12 44 v cc 77 int2/inta0 _n/pwd/pio31 11 ad5 45 a17/pio7 78 int1/select_n 12 gnd 46 a16 79 int0 13 ao13 47 a15 80 ucs_n/once1_n 14 ad6 48 a14 81 lcs_n/once0_n 15 v cc 49 a13 82 pcs6_n/a2/pio2 16 ao14 50 a12 83 pcs5_n/a1/pio3 17 ad7 51 a11 84 v cc 18 ao15 52 a1 0 85 pcs3_n/rts1_n/rtr1_n/pio19 19 s6/lock_n/clkdiv2 _n /pio29 53 a9 86 pcs2_n/cts1_n/enrx1_n/pio18 20 uzi_n/pio26 54 a8 87 gnd 21 txd1/pio27 55 a7 88 pcs1_n/pio17 22 rxd1/pio28 56 a6 89 pcs0_n/pio16 23 cts0_n/enrx0_n/pio21 57 a5 90 v cc 24 r xd0/pio23 58 a4 91 mcs2_n/pio24 25 txd0/pio22 59 a3 92 mcs3_n/rfsh_n/pio25 26 rts0_n/rtr0_n/pio20 60 a2 93 gnd 27 rfsh2_n/aden_n 61 v cc 94 res_n 28 wr_n 62 a1 95 tmrin1/pio0 29 rd_n 63 a0 96 tmrout1/pio1 30 ale 64 gnd 97 tmrout0/pio10 31 ardy 65 gnd 98 tmrin0/pio11 32 s2_n 66 wb_n 99 drq1/int6/pio13 33 s1_n 67 hlda 100 drq0/int5/pio12 34 s0_n ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 22 of 154 1 - 888 - 824 - 4184 table 4 . ia188es tqfp alphabetic pin listing name pin name pin name pin a0 63 ao13 13 pcs2_n/cts 1_n/enrx1_n/pio18 86 a1 62 ao14 16 pcs3_n/rts1_n/rtr1_n/pio19 85 a2 60 ao15 18 pcs5_n/a1/pio3 83 a3 59 ardy 30 pcs6_n/a2/pio2 82 a4 58 clkouta 39 rd_n 29 a5 57 clkoutb 40 res_n 94 a6 56 cts0_n/enrx0_n/pio21 23 rfsh_n/aden_n 27 a7 55 d en_n/ds_n/pio5 72 rts0_n/rtr0_n/pio20 26 a8 54 drq0/int5/pio12 100 rxd0/pio23 24 a9 53 drq1/int6/pio13 99 rxd1/pio28 22 a10 52 dt/r_n/pio4 71 s0_n 34 a11 51 gnd 12 s1_n 33 a12 50 gnd 35 s2_n 32 a13 49 gnd 41 s6/lock_n/clkdiv2 _n /pio29 19 a14 48 gnd 64 srdy/pio6 69 a15 47 gnd 65 tmrin0/pio11 98 a16 46 gnd 87 tmrin1/pio0 95 a17/pio7 45 gnd 93 tmrout0/pio10 97 a18/pio8 43 hlda 67 tmrout1/pio1 96 a19/pio9 42 hold 68 txd0/pio22 25 ale 30 int0 79 txd1/pio27 21 ad0 1 in t1/select_n 78 ucs_n/once1_n 80 ad1 3 int2/inta0_n/pwd/pio31 77 uzi_n/pio26 20 ad2 5 int3/inta1_n/irq 76 v cc 15 ad3 7 int4/pio30 75 v cc 38 ad4 9 lcs_n/once0_n 81 v cc 44 ad5 11 mcs0_n/pio14 73 v cc 61 ad6 14 mcs1_n/pio15 74 v cc 84 ad7 1 7 mcs2_n/pio24 91 v cc 90 ao8 2 mcs3_n/rfsh_n/pio25 92 wb_n 66 ao9 4 nmi 70 wr_n 28 ao10 6 pcs0_n/pio16 89 x1 36 ao11 8 pcs1_n/pio17 88 x2 37 ao12 10 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 23 of 154 1 - 888 - 824 - 4184 2.1.3 tqfp physical dimensions the physical dimensions for the tqfp are as shown in figure 3. figure 3 . tqfp package dimensions legend: symbol millimeter inch min nom max min nom max a C C 1.2 0 C C 0.047 a1 0.0 5 C 0.15 0.0 0 2 C 0.006 a2 0.95 1.00 1.05 0. 0 37 0.039 0.041 b 0.17 0.20 0.27 0.007 0.008 0.011 c 0.09 C 0.20 0.004 C 0.008 d 16.00 b sc. 0.630 b sc. d1 14.00 b sc. 0.551 b sc. d2 1 2 . 0 0 0.472 e 0.5 0 bsc . 0.02 bsc . e 16.00 b sc. 0.630 b sc. e1 14.00 b sc. 0.551 bsc. e2 12.00 0.472 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.0 39 ref r1 0 . 08 C C 0.003 C C r2 0.08 C 0.2 0 0.003 C 0.008 s 0.2 0 C C 0.008 C C 0 3.5 7 0 3.5 7 1 0 C C 0 C C 2 11 12 13 11 12 13 3 11 12 13 11 12 13 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 note : control dimensions are in millimeters. ? s e a t i n g p l a n e ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 24 of 154 1 - 888 - 824 - 4184 2.1.4 ia186es pqfp package the pinout for the ia186es pqfp package is as shown in figure 4. the corresponding pinout is provided in tables 5 and 6. figure 4 . ia186es pqfp packag e diagram ? c t s 0 _ n / e n r x 0 _ n / p i o 2 1 r x d 1 / p i o 2 8 t x d 1 / p i o 2 7 u z i _ n / p i o 2 6 s 6 / l o c k _ n / c l k d i v 2 _ n / p i o 2 9 a d 1 5 a d 7 a d 1 4 v c c a d 6 a d 1 3 g n d a d 5 a d 1 2 a d 4 a d 1 1 a d 3 a d 1 0 a d 2 a d 9 i a 1 8 6 e s t q f p a d 1 a d 8 a d 0 d r q 0 / i n t 5 / p i o 1 2 d r q 1 / i n t 6 / p i o 1 3 t m r i n 0 / p i o 1 1 t m r o u t 0 / p i o 1 0 t m r o u t 1 / p i o 1 t m r i n 1 / p i o 0 r e s _ n g n d m c s 3 _ n / r f s h _ n / p i o 2 5 m c s 2 _ n / p i o 2 4 v c c p c s 0 _ n / p i o 1 6 p c s 1 _ n / p i o 1 7 g n d p c s 2 _ n / c t s 1 _ n / e n r x 1 _ n / p i o 1 8 p c s 3 _ n / r t s 1 _ n / r t r 1 _ n / p i o 1 9 v c c p c s 5 _ n / a 1 / p i o 3 p c s 6 _ n / a 2 / p i o 2 l c s _ n / o n c e 0 _ n u c s _ n / o n c e 1 _ n i n t 0 i n t 1 / s e l e c t _ n i n t 2 / i n t a 0 _ n / p w d / p i o 3 1 i n t 3 / i n t a 1 _ n / i r q i n t 4 / p i o 3 0 m c s 1 _ n / p i o 1 5 r x d 0 / p i o 2 3 t x d 0 / p i o 2 2 r t s 0 _ n / r t r 0 _ n / p i o 2 0 b h e _ n / a d e n _ n w r _ n r d _ n a l e a r d y s 2 _ n s 1 _ n s 0 _ n g n d x 1 x 2 v c c c l k o u t a c l k o u t b g n d a 1 9 / p i o 9 a 1 8 / p i o 8 v c c a 1 7 / p i o 7 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 v c c a 1 a 0 g n d w h b _ n w l b _ n h l d a h o l d s r d y / p i o 6 n m i d t / r _ n / p i o 4 d e n _ n / d s _ n / p i o 5 m c s 0 _ n / p i o 1 4 i a 1 8 6 e s p q f p ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 25 of 154 1 - 888 - 824 - 4184 table 5 . ia186es pqfp numeric pin listing pin name pin name pin name 1 rxd0/pio23 35 a4 68 mcs2_n/pio24 2 txd0/pio22 36 a3 69 mcs3_n/rfsh_n/pio25 3 rts0_n/rtr0_n/pio20 37 a2 70 gnd 4 bhe_n/aden_n 38 v cc 71 res_n 5 wr_n 39 a1 72 tmrin1/pio 0 6 rd_n 40 a0 73 tmrout1/pio1 7 ale 41 gnd 74 tmrout0/pio10 8 ardy 42 whb_n 75 tmrin0 /pio11 9 s2_n 43 wlb_n 76 drq1/int6/pio13 10 s1_n 44 hlda 77 drq0/int5/pio12 11 s0_n 45 hold 78 ad0 12 gnd 46 srdy /pio6 79 ad8 13 x1 47 nmi 80 ad1 14 x2 48 dt/r_n/pio4 81 ad9 15 v cc 49 den_n/ds_n/pio5 82 ad2 16 clkouta 50 mcs0_n/pio14 83 ad10 17 clkoutb 51 mcs1_n/pio15 84 ad3 18 gnd 52 int4/pio30 85 ad11 19 a19/pio9 53 int3/inta1_n/irq 86 ad4 20 a18/pio8 54 int2/inta0_n/pwd/pio31 87 ad12 21 v cc 55 int1/select_n 88 ad5 22 a17/pio7 56 int0 89 gnd 23 a16 57 ucs_n/once1_n 90 ad13 24 a15 58 lcs_n/once0_n 91 ad6 25 a14 59 pcs6_n/a2/pio2 92 v cc 26 a13 60 pcs5_n/a1/pio3 93 ad14 27 a1 2 61 v cc 94 ad7 28 a11 62 pcs3_n/rts1_n/rtr1_n/pio19 95 ad15 29 a10 63 pcs2_n/cts1_n/enrx1_n / pio 18 96 s6/lock_n/clkdiv2_n/pio29 30 a9 64 gnd 97 uzi_n/pio26 31 a8 65 pcs1_n/pio17 98 txd1/pio27 32 a7 66 pcs0_n/pio16 99 rxd1/pio28 33 a6 67 v cc 100 cts0_n/enrx0_n/pio21 34 a5 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 26 of 154 1 - 888 - 824 - 4184 table 6 . ia186es p qfp alphabetic pin listing name pin name pin name pin a0 40 ad14 93 pcs2_n/cts1_n/enrx1_n/pio18 63 a1 39 ad15 95 pcs3_n/rts1_n/rtr1_n/pio19 62 a2 37 ale 7 pcs5_n/a1/pio3 60 a3 36 ardy 8 pcs6_n/a2/pio2 59 a4 35 bhe_n/aden_n 4 rd_n 6 a5 34 clkouta 16 res_n 71 a6 33 clkoutb 17 rts0_n/rtr0_n/pio20 3 a7 32 cts0_n/enrx0_n/pio21 100 rxd0/pio23 1 a8 31 den_n/ds_n/pio5 49 rxd1/pio28 99 a9 30 dr q0/int5/pio12 77 s0_n 11 a10 29 drq1/int6/pio13 76 s1_n 10 a11 28 dt/r_n/pio4 48 s2_n 9 a12 27 gnd 12 s6/lock_n/clkdiv2/pio29 96 a13 26 gnd 18 srdy/pio6 46 a14 25 gnd 41 tmrin0/pio11 75 a15 24 gnd 64 tmrin1/pio0 72 a16 23 gnd 70 tm rout0/pio10 74 a17/pio7 22 gnd 89 tmrout1/pio1 73 a18/pio8 20 hlda 44 txd0/pio22 2 a19/pio9 19 hold 45 txd1/pio27 98 ad0 78 int0 56 ucs_n/once1_n 57 ad1 80 int1/select_n 55 uzi_n/pio26 97 ad2 82 int2/inta0_n/pwd/pio31 54 v cc 15 ad3 8 4 int3/inta1_n/irq 53 v cc 21 ad4 86 int4/pio30 52 v cc 38 ad5 88 lcs_n/once0_n 58 v cc 61 ad6 91 mcs0_n/pio14 50 v cc 67 ad7 94 mcs1_n/pio15 51 v cc 92 ad8 79 mcs2_n/pio24 68 whb_n 42 ad9 81 mcs3_n/rfsh_n/pio25 69 wlb_n 43 ad10 83 nmi 4 7 wr_n 5 ad11 85 pcs0_n/pio16 66 x1 13 ad12 87 pcs1_n/pio17 65 x2 14 ad13 90 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 27 of 154 1 - 888 - 824 - 4184 2.1.5 ia188es pqfp package the pinout for the ia188es pqfp package is as shown in figure 5. the corresponding pinout is provided in tables 7 and 8. figure 5 . ia188es pqfp package diagram ? c t s 0 _ n / e n r x 0 _ n / p i o 2 1 r x d 1 / p i o 2 8 t x d 1 / p i o 2 7 u z i _ n / p i o 2 6 s 6 / l o c k _ n / c l k d i v 2 _ n / p i o 2 9 a o 1 5 a d 7 a o 1 4 v c c a d 6 a o 1 3 g n d a d 5 a o 1 2 a d 4 a o 1 1 a d 3 a o 1 0 a d 2 a o 9 i a 1 8 6 e s t q f p a d 1 a o 8 a d 0 d r q 0 / i n t 5 / p i o 1 2 d r q 1 / i n t 6 / p i o 1 3 t m r i n 0 / p i o 1 1 t m r o u t 0 / p i o 1 0 t m r o u t 1 / p i o 1 t m r i n 1 / p i o 0 r e s _ n g n d m c s 3 _ n / r f s h _ n / p i o 2 5 m c s 2 _ n / p i o 2 4 v c c p c s 0 _ n / p i o 1 6 p c s 1 _ n / p i o 1 7 g n d p c s 2 _ n / c t s 1 _ n / e n r x 1 _ n / p i o 1 8 p c s 3 _ n / r t s 1 _ n / r t r 1 _ n / p i o 1 9 v c c p c s 5 _ n / a 1 / p i o 3 p c s 6 _ n / a 2 / p i o 2 l c s _ n / o n c e 0 _ n u c s _ n / o n c e 1 _ n i n t 0 i n t 1 / s e l e c t _ n i n t 2 / i n t a 0 _ n / p w d / p i o 3 1 i n t 3 / i n t a 1 _ n / i r q i n t 4 / p i o 3 0 m c s 1 _ n / p i o 1 5 r x d 0 / p i o 2 3 t x d 0 / p i o 2 2 r t s 0 _ n / r t r 0 _ n / p i o 2 0 b h e _ n / a d e n _ n w r _ n r d _ n a l e a r d y s 2 _ n s 1 _ n s 0 _ n g n d x 1 x 2 v c c c l k o u t a c l k o u t b g n d a 1 9 / p i o 9 a 1 8 / p i o 8 v c c a 1 7 / p i o 7 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 v c c a 1 a 0 g n d g n d w b _ n h l d a h o l d s r d y / p i o 6 n m i d t r / r _ n / p i o 4 d e n _ n / d s _ n / p i o 5 m c s 0 _ n / p i o 1 4 i a 1 8 8 e s p q f p ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 28 of 154 1 - 888 - 824 - 4184 table 7 . ia188es pqfp numeric pin listing pin name pin name pin name 1 rxd0/pio23 35 a4 68 mcs2_n/pio24 2 txd0/pio22 36 a3 69 mcs3_n/rfsh_n/ pio25 3 rts0_n/rtr0_n/pio20 37 a2 70 gnd 4 bhe_n/aden_n 38 v cc 71 res_n 5 wr_n 39 a1 72 tmrin1/pio0 6 rd_n 40 a0 73 tmrout1/pio1 7 ale 41 gnd 74 tmrout0/pio10 8 ardy 42 gnd 75 tmrin0 /pio11 9 s2_n 43 wb_n 76 drq1/int6/pio13 10 s1_n 44 hlda 77 drq0/int5/pio12 11 s0_n 45 hold 78 ad0 12 gnd 46 srdy/pio6 79 ao8 13 x1 47 nmi 80 ad1 14 x2 48 dt/r_n/pio4 81 ao9 15 v cc 49 den_n/ds_n/pio5 82 ad2 16 clkouta 50 mcs0_n/pio14 83 ao10 17 clkoutb 51 mcs1_n/pio15 84 ad3 18 gnd 52 int4/pio30 85 ao11 19 a19/pio9 53 int3/inta1_n/irq 86 ad4 20 a18/pio8 54 int2/inta0_n/pwd/pio31 87 ao12 21 v cc 55 int1/select_n 88 ad5 22 a17/pio7 56 int0 89 gnd 23 a16 57 ucs_n/once1_n 90 ao13 24 a15 58 lcs_n/once0_n 91 ad6 25 a14 59 pcs6_n/a2/pio2 92 v cc 26 a13 60 pcs5_n/a1/pio3 93 ao14 27 a12 61 v cc 94 ad7 28 a11 62 pcs3_n/rts1_n/rtr1_n/pio19 95 ao15 29 a10 63 pcs2_n/cts1_n/enrx1_n/pio18 96 s6/lock_n/clkdiv2_n/pio29 30 a9 64 gnd 97 uzi_n/pio26 31 a8 65 pcs1_n/pio 17 98 txd1/pio27 32 a7 66 pcs0_n/pio16 99 rxd1/pio28 33 a6 67 v cc 100 cts0_n/enrx0_n/pio21 34 a5 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 29 of 154 1 - 888 - 824 - 4184 table 8 . ia188es pqfp alphabetic pin listing name pin name pin name pin a0 40 ao13 90 pcs2_n/cts1_n/enrx1_n/pio 18 63 a1 39 ao14 93 pcs3_n/rts1_n/rtr1_n/pio19 62 a2 37 ao15 95 pcs5_n/a1/pio3 60 a3 36 ardy 8 pcs6_n/a2/pio2 59 a4 35 bhe_n/aden_n 4 rd_n 6 a5 34 clkouta 16 res_n 71 a6 33 clkoutb 17 rts0_n/rtr0_n/pio20 3 a7 32 cts0_n/enrx0_n/pio2 1 100 rxd0/pio23 1 a8 31 den_n/ds_n/pio5 49 rxd1/pio28 99 a9 30 drq0/int5/pio12 77 s0_n 11 a10 29 drq1/int6/pio13 76 s1_n 10 a11 28 dt/r_n/pio4 48 s2_n 9 a12 27 gnd 12 s6/lock_n/clkdiv2/pio29 96 a13 26 gnd 18 srdy/pio6 46 a14 25 gnd 41 tmrin0/pio11 75 a15 24 gnd 42 tmrin1/pio0 72 a16 23 gnd 64 tmrout0/pio10 74 a17/pio7 22 gnd 70 tmrout1/pio1 73 a18/pio8 20 gnd 89 txd0/pio22 2 a19/pio9 19 hlda 44 txd1/pio27 98 ad0 78 hold 45 ucs_n/once1_n 57 ad1 80 int0 56 u zi_n/pio26 97 ad2 82 int1/select_n 55 v cc 15 ad3 84 int2/inta0_n/pwd/pio31 54 v cc 21 ad4 86 int3/inta1_n/irq 53 v cc 38 ad5 88 iint4/pio30 52 v cc 61 ad6 91 lcs_n/once0_n 58 v cc 67 ad7 94 mcs0_n/pio14 50 v cc 92 ale 7 mcs1_n/pio15 51 w b_n 43 ao8 79 mcs2_n/pio24 68 wr_n 5 ao9 81 mcs3_n/rfsh_n/pio25 69 x1 13 ao10 83 nmi 47 x2 14 ao11 85 pcs0_n/pio16 66 ao12 87 pcs1_n/pio17 65 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 30 of 154 1 - 888 - 824 - 4184 2.1.6 pqfp physical dimensions the physical dimensions for the pqfp are as shown in figure 6. figure 6 . pqfp package dimensions legend symbol millimeter inch min nom max min nom max a C C 3.40 C C 0.134 a 1 0.25 C C 0.010 C C a 2 2.73 2.85 2.97 0.107 0.112 0.117 b 0.25 0.30 0.38 0.010 0.012 0.015 b 1 0.22 0.30 0.33 0.009 0.012 0.013 c 0.13 0.15 0.23 0.005 0.006 0.009 c 1 0.11 0.15 0.17 0.004 0.006 0.007 d 23.00 23.20 23.40 0.906 0.913 0.921 d 1 19.90 20.00 20.10 0.783 0.787 0.791 e 17.00 17.20 17.40 0.669 0.677 0.685 e 1 13.90 14.00 14.10 0.547 0.551 0.555 e 0.65 bsc . 0.026 bsc . l 0.73 0.88 1.03 0.029 0.035 0.041 l 1 1.60 bsc . 0.063 bsc . r 1 0.13 C C 0.005 C C r 2 0.13 C 0.30 0.005 C 0.012 s 0.20 C C 0.008 C C y C C 0.10 C C 0.004 0 C 7 0 C 7 1 0 C C 0 C C 2 9 10 11 9 10 11 3 9 10 11 9 10 11 notes : 1. dimensions d 1 and e 1 do not include mold protrusion , b ut mold mismatch is included. allowable protrusion is 0.25mm/0.010 per side. 2. dimension b does not include dambar protrusion. allowable protrusion is 0.08mm/0.003 total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 3. controlling dimension: millimeter. ? s e e d e t a i l a s e e d e t a i l b d e t a i l a d e t a i l b p i n 1 i n d i c a t o r p l a t i n g ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 31 of 154 1 - 888 - 824 - 4184 2.2 pin descriptions 2.2.1 a19/pio9, a18/pio8, a17/pio7, a16 C a0 address bus (synchronous outputs with t ristate) these pins are the systems source of non - multiplexed i/o or memory addresses and occur a half clkouta cycle before the multiplexed address/data bus ( ad15 C ad0 for the ia186es or ao15 C ao8 and ad7 C ad0 for the ia 188es). the address bus is tristated d uring a bus hold or reset. 2.2.2 ad15 C ad8 ( ia186es ) address/data bus (level - sensitive synchronous inouts with tristate) these pins are the systems source of time - multiplexed i/o or memory addresses and data. the address functio n of these pins may be disabled (see bhe_n/aden_n pin description ). if the address function of these pins is enabled, the address will be present on this bus during t 1 of the bus cycle and data will be present during t 2 , t 3 , and t 4 of the same bus cycle . if whb_n is not a ctive, these pins are tristated during t 2 , t 3 , and t 4 of the bus cycle. the address/data bus is tristated during a bus hold or reset. these pins may be used to load the internal reset configuration register ( rescon, offset 0f6h ) with configuration data during a por . 2.2.3 ao1 5 C ao8 ( ia188es ) address bus (level - sensitive synchronous outputs with tristate) the address bus will contain valid high order address bits during the bus cycle (t 1 , t 2 , t 3 , and t 4 ) if the bu s is enabled by the ad bit in the upper and lower memory chip select registers ( umcs, offset 0a0h , and lmcs, offset 0a2h ). these pins are combined with ad7 C ad0 to complete the multiplexed address bus and are tristated during a bus hold or reset condition. 2.2.4 ad7 C ad0 address/data bus (level - sensitive synchronous inouts with tristate) these pins are the systems source of time - multiplexed low order byte of the addresses for i/o or memory and 8 - bit da ta. the low order address byte will be present on this bus during t 1 of the bus cycle and the 8 - bit data will be present during t 2 , t 3 , and t 4 of the same bus cycle. the address function of these pins may be disabled ( see bhe_n/aden_n pin description ). ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 32 of 154 1 - 888 - 824 - 4184 if wlb_n is not active, these pins are tristated during t 2 , t 3 , and t 4 of the bus cycle. the address/data bus is tristated during a bus hold or reset. 2.2.5 ale address latch enable (synchronous output) this signal indicates the presence of an address on the address bus ( ad15 C ad0 for the ia186es or ao15 C ao8 and ad7 C ad0 for the ia 188es), which is guaranteed to be valid on the falling edge of ale . in once mode, this pin is tristated but not during bus hold or reset. 2.2.6 ardy asynchrono us ready (level - sensitive asynchronous input) this asynchronous signal provides an indication to the microcontroller that the addressed i/o device or memory space will complete a data transfer. this active high signal is asynchronous with respect to clkou ta . if the falling edge of ardy is not synchronized to clkouta , an additional clock cycle may be added. the ardy or srdy must be synchronized to clkouta to guarantee the number of inserted wait states. the ardy should be tied high to maintain a permanent assertion of the ready condition. on the other hand, if the ardy signal is not used by the system, it should be tied low, which passes control to the srdy signal. 2.2.7 bhe_n/aden_n ( ia186es only ) bus high enable (synchronous output with tristate)/address enab le (input with internal pullup) the bhe_n C bhe_n and address bit ad0 or a0 inform the system which bytes of the data bus (upper, lower, or both) are involved in the current memory access bus cycle, as shown in table 9 . table 9 . b us cycle types for bhe_n and ad0 bhe_n ad0 type of bus cycle 0 0 word transfer 0 1 high byte trans fer (b its [ 15 C 8 ] ) 1 0 low byte transfer (bits [ 7 C 0 ] ) 1 1 refresh the bhe_n does not require latching and during bus hold and reset is tristated. it is asserted during t 1 and remains so through t 3 and t w . the high - and low - byte write enable functions of bhe_n and ad0 are performed by whb_n and wlb_n , respectively. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 33 of 154 1 - 888 - 824 - 4184 when using the ad bus, dram refresh cycles are indicated by bhe_n/aden_n and ad0 , both being high. during refresh cycles, the a and ad busses may not have the same address during the address phase of the ad bus cycle. this would necessitate the use of ad0 as a determinant for the refresh cycle, rather than a0. an additional signal is use d for p seudo - static ram ( psram ) refreshes (see mcs3_n/rfsh_n pin description ) , aden_n. there is a weak internal pullup on bhe_n/aden_n , eliminating the need for an external pullup and reducing power consumption. holding aden_n high or letting it float during power - on reset (por) , passes control of the address function of the ad bus ( ad15 C ad0 ) during lcs and ucs bus cycles from aden_n to the disable address ( da ) bit in lmcs and umcs registers. when the address function is selec ted, the memory address is placed on the a19 C a0 pins. when holding aden_n low during por , both the address and data are driven onto the ad bus independently of the da bit setting. this pin is normally sampled on the rising edge of res_n and the conditio n of s6 and uzi_n default to their normal functions. 2.2.8 clkouta cloc k output a (synchronous output) this pin is the internal clock output t o the system. bits [ 9 C 8 ] and bits [ 2 C 0 ] of the system configuration (syscon) register control the output of this pin, which may be disabled, output the pll frequency, or output the power save frequency (internal processor frequency after divisor). the clkouta may be used as a full - speed clock sour ce in power - save mode. the ac timing specifications that are clock - related refer to clkouta , which remains active during reset and hold conditions. 2.2.9 clkoutb clock output b (synchronous output) this pin is an additional clock out put to the system with and output delayed with respect to clkouta. bits [ 11 C 10 ] and bits [ 2 C 0 ] of the syscon register control the output of this pin, which may be disabled, output the pll frequency, or may output the power save frequency (internal processor frequency after divisor). the clkoutb may be used as a full - speed clo ck source in power - save mode a nd remains active during reset and hold conditions. 2.2.10 cts0_n/enrx0_n/pio21 clear - to - send 0/enable - receive - request 0 (both are asynchronous inputs) the cts0_n is the clear - to - send signal for asynchronou s serial port 0, provided that b it [ 4 ] (enrx0) in the aux con register is 0, and b it [ 9 ] (fc) in the sp0ct register is 1. the cts0_n controls the transmission of data from asynchronous serial port 0. when it is asserted, the transmitter begins transmitting the next frame of data. when it is not asserted, the d ata to be transmitted is held in the transmit register. this signal is checked only at the start of data frame transmission. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 34 of 154 1 - 888 - 824 - 4184 the enrx0_n is the enable - receiver - request for a synchronous serial port 0 when b it [ 4 ] (enrx0) in the auxcon register is 1, and b i t [ 9 ] (fc) in the sp0ct register is 1, and it enables the asynchronous serial port receiver. 2.2.11 den_n/ds_n/pio5 data enable /data strobe (both are synchronous outputs with tristate) den_n is asserted during i/o, memory, and interrupt acknowledge processes and is deasserted when dt/r_n undergoes a change of state. it is tristated for a bus hold or reset. after reset, this pin defaults to den_n. the data strobe ds_n is used under conditions in which a write cycle has the same timing as a read cycle. it is use d with other control signals to interface with 68 - k byte - type peripherals without further system interface logic. when it is asserted, addresses are valid. d uring a write, the data is valid, while during a read , data may be applied to the ad bus. 2.2.12 drq0/int 5/pio12 dma request 0 (synch ronous level - sensitive input)/ maskable interrupt request 5 (asynchronous edge - triggered input) the drq0 is an external device that is ready for dma ch annel 0 to carry out a transfer. it indicates to the microcontroller this rea diness on this pin. it is not latched and must remain asserted until it is dealt with. if dma channel 0 is not required, int5 may be used as an extra interrupt request sharing the dma0 interrupt type (0ah) and control bits. it is not latched and must rem ain asserted until it is dealt with. 2.2.13 drq1/int6/pio13 dma request 1 (synch ronous level - sensitive input)/ maskable interrupt request 6 (asynchronous edge - triggered input) the drq1 is a n external device that is ready for dma channel 1 to carry out a t ransfer. it indicates to the microcontroller this readiness on this pin. it is not latched and must remain asserted until it is dealt with. if dma channel 1 is not required, int6 may be used as an extra interrupt request sharing the dma1 interrupt type (0bh) and control bits. it is not latched and must remain asserted until it is dealt with. 2.2.14 dt/r_n/pio4 data transmit or receive (sy nchronous output with tristate) the microntroller transmits data when dt/r_n is pulled high and receives data when this pin is pulled low. it floats during a reset or bus hold condition. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 35 of 154 1 - 888 - 824 - 4184 2.2.15 gnd ground depending on the package , six or seven pins connect the microcontroller to the system ground. 2.2.16 h lda bus hold acknowledge (synchronous output) this pin is pulled high to signal the system that the microntroller has relinquished control of the local bus, in response to a high on the hold signal by an external bus master, after the microcontroller has completed the current bus cycle. the assertion of hlda is accompanied by the tristating of den_n , rd_n, wr_n, s2 C s0, ad15 C ad0, s6, a19 C a0, bhe_n, whb_n, wlb_n, and dr/r_n , followed by the driving high of the chip selects ucs_n, lcs_n, mcs3_n C mcs0_n, pcs6_n C pcs5_n, and pcs3_n C pcs0_n . the external bus master releases control of the local bus by the de assertion of hold that in turn induces the microcontroller to deassert the hlda . the microcontroller may take control of the bus if necessary (to execute a refresh for example), by deasserting hlda without the bus master first deasserting hold . this requ ires that the external bus master must be able to deassert hold to permit the microcontroller to access the bus. 2.2.17 int0 maskable interrupt request 0 (asynchronous input) the int0 pin provides an indication that an interrupt request has occurred, and provided that int0 is not masked, program execution will continue at the location specified by the int0 vector i n the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and may be edge - or level - triggered. to e nsure that it is recognized, the assertion of the interrupt request must be maintained until it is handled . 2.2.18 int1/select_n maskable interrupt request 1/slave select (both are asynchronous inputs) the int1 pin provides an indication that an interrupt request has occurred. p rovided that int1 is not masked, program execution will continue at the location specified by the int1 vector in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and may be edge - o r level - triggered. to ensure that it is recognized , the assertion of the interrupt request must be maintained until it is handled . th e select_n pin provides an indication to the microcontroller that an interrupt type has been placed on the address/data bu s when the internal interrupt control unit is slaved to an external interrupt controller. however , before this occurs , the int0 pin must have indicated an interrupt request has occurred. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 36 of 154 1 - 888 - 824 - 4184 2.2.19 int2/inta0_n/pwd/pio31 maskable interrupt request 2 (asynchronous in put) /interrupt ackno wledge 0 (synchronous output)/ p ulse width demodulator (schmitt trigger input) the int2 pin provides an indication that an interrupt request has occurred. provided that int1 is not masked, program execution will continue at the location specified by the int1 vector i n the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and may be edge - or level - triggered. to ensure that it is recognized , the assertion of the interrupt request must be maintained until it is handled. when int0 is configured to be in cascade mode, int2 changes its function to inta0_n . t h e inta0_n function indicates to the system that the microcontroller requires an interrupt type in response to the interrupt request i nt0 when the microcontrollers interrupt control unit is in cascade mode. the pwd processes a signal via the schmitt trigger when pulse width demodulation is enabled. it drives tim rin0 and int2 and its inverse signal drives tim rin1 and int4. provided tha t int2 and int4 are enabled and timer0 and timer1 are configured correctly, the pulse width of the alternating signal on pwd may be calculated from the values in timer0 and timer1 . while in pwd mode, tm rin0 / pio11 , tm rin1/pio0 , and int4/pio31 signals are fr ee for use as pio s or may be ignored. the level on this pin is held in the pio data register in the pio31 position, just as if it were a pio. 2.2.20 int3/inta1_n/irq maskable interrupt request 3 (asynchronous i nput)/ interrupt ackno wledge 1 (synchronous output)/ i nterrupt a cknowledge (synchronous output) the int3 pin provides an indication that an interrupt request has occurred. p rovided that int3 is not masked, program execution will continue at the location specified by the int3 vector in the interrupt vector ta ble. although interrupt requests are asynchronous, they are synchronized internally and may be edge - or level - triggered. to ensure that it is recognized , the assertion of the interrupt request must be maintained until it is handled . when int1 is configu red to be in cascade mode, int3 changes its function to inta1_n . the inta1_n function indicates to the system that the microcontroller requires an interrupt type in response to the interrupt request int1 when the microcontrollers interrupt control unit is in cascade mode. with the interrupt control unit of the microcontroller in slave mode, the signal on the irq pin allows the microcontroller to output an interrupt request to the external master interrupt controller. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 37 of 154 1 - 888 - 824 - 4184 2.2.21 int4/pio30 maskable interrupt request 4 (asynchronous input) the int4 pin provides an indication that an interrupt request has occurred. and provided that int4 is not masked, program execution will continue at the location specified by the int4 vector in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and may be edge - or level - triggered. to ensure that it is recognized, the assertion of the interrupt request must be maintained until it is handled. in the case where pwd mode is selec ted, int4 indicates a high - to - low transition of the pwd signal. conversely, in the event that pwd mode is not selected, int4 may be used as a pio. 2.2.22 lcs_n/once0_n lower memory chip select (synchronous output with internal pullup)/ once mode request (input) t he lcs_n pin provides an indication that a memory access is in progress to the lower memory block. the size of the lower memory block and its base address are programmable, with the size adjustable up to 512 kbytes. the lcs_n may be configured for either an 8 - or 16 - bit bus width for the ia186es microcontroller by the auxiliary configuration register (auxcon b it [ 2 ] ) and is held high during bus hold. th e once0_n pin ( on c ircuit e mulation ) and its companion pin once1_n define the microcontroller mode duri ng reset. these two pins are sampled on the rising edge of res_n and if both are asserted low the microcontroller starts in once mode, else it starts normally. in once mode , all pins are tristated and remain so until a subsequent reset. to prevent the m icrocontroller from entering once mode inadvertently, this pin has a weak pullup that is only present during reset. finally this pin is not tristated during bus hold. 2.2.23 mcs0_n/pio14 midrange memory chip select (synchronous output with internal pullup) the m cs0_n pin provides an indication that a memory access is in progress to the midrange memory block. the size of the midrange memory block and its base address are programmable. the mcs0_n may be configured for either an 8 - or 16 - bit bus width for the ia18 6es microcontroller by the auxiliary configuration register (auxcon b it [ 1 ] ) and is held high during bus hold. the mcs0_n may be programmed as the chip select for the whole middle chip select address range. furthermore, this pin has a weak pullup that is only present during reset. 2.2.24 mcs2_n C mcs1_n (pio24 C pio 15) midrange memory chip selects (synchronous outputs with internal pullup) the mcs2_n and mcs1_n pins provide an indication that a memory access is in progress to the second or third midrange memory b lock. the size of the midrange memory block and its base address are programmable. the mcs2_n and mcs1_n may be configured for either an 8 - or 16 - bit bus width for the ia186es microcontroller by the auxiliary configuration register (auxcon b it [ 1 ] ) and a re held high during bus hold. furthermore, these pins have weak pullups that are ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 38 of 154 1 - 888 - 824 - 4184 present only during reset. if mcs0_n has been programmed as the chip select for the whole middle chip select address range, these pins may be used as pios. 2.2.25 mcs3_n/rfsh_n/pio 25 midrange memory chip select (synchronous outputs with internal pullup)/ automatic refresh (synchronous output) the mcs3_n pin provides an indication that a memory access is in progress to the fourth region of the midrange memory block. the size of the m idrange memory block and its base address are programmable. the mcs3_n may be configured for either an 8 - or 16 - bit bus width for the ia186es microcontroller by the auxiliary configuration register (auxcon b it [ 1 ] ) and is held high during bus hold. if mc s0_n has been programmed as the chip select for the whole middle chip select address range, this pin may be used as pio. furthermore, this pin has a weak pullup that is only present during reset. th e rfsh_n signal is timed for auto refresh to psram or d ram devices. the refresh pulse is only output when the psram or dram m ode bit is set (edram register b it [ 15 ] ). this pulse is of 1.5 clock pulse duration with the rest of the refresh cycle made up of a deassertion period such that the overall refresh tim e is met. finally this pin is not tristated during a bus hold. 2.2.26 n mi nonmaskable interrupt (synchronous edge - sensitive input) this is the highest priority interrupt signal and cannot be masked, unlike int6 C int0 . program execution is transferred to the nonma skable interrupt vector in the interrupt vector table, upon the assertion of this interrupt (transition from low to high ), and this interrupt is initiated at the next instruction boundary. for recognition to be assured, the nmi pin must be held high for a t least a clkouta period. the nmi is not involved in the priority resolution process, which deals with the maskable interrupts and does not have an associated interrupt flag. this allows for a new nmi request to interrupt an nmi service routine that is already underway. the interrupt flag if is cleared, disabling the maskable interrupts, when an interrupt is taken by the processor. if, during the nmi service routine, the maskable interrupts are re - enabled, by use of sti instruction for example, the pri ority resolution of maskable interrupts will be unaffected by the servicing of the nmi . for this reason , it is strongly recommended that the nmi interrupt service routine does not enable the maskable interrupts. 2.2.27 pcs1_n C pcs0_n (pio17 C pio16) peripheral chip selects 1 C 0 (synchronous outputs) these pins provide an indication that a memory access is under way for the second and first regions , respectively , of the peripheral memory block (i/o or memory address space). the base address of the peripheral memory b lock is programmable. the pcs3_n C pcs0_n are held high ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 39 of 154 1 - 888 - 824 - 4184 during both bus hold and reset. these outputs are asserted with the ad address bus over a 256 byte range each. 2.2.28 pcs2_n/cts1_n/enrx1_n/pio18 peripheral chip select 2 (synchronous output)/ clear - t o - send 1 (asynchronous input)/ enable - receiver - request 1 (asynchronous input) t h e pcs2_n signal provides an indication that a memory access is under way for the third region of the peripheral memory block (i/o or memory address space). the base address of the peri pheral memory block is programmable. the pcs2_n is held high during both bus hold and reset. this output is asserted with the ad address bus over a 256 - byte range. the cts1_n is the clear - to - s end signal for asynchronous serial port 1 when the enrx1 bit ( b it [ 6 ] ) in the auxiliary control register (auxcon) is 0 and hardware flow control is enabled for this port (fc bit [b it ( 9 )] in the serial port 1 control register [sp1ct] ) . this signal controls the transmission of data from the serial port transmit regis ter 1. when this signal is asserted, the transmitter begins sending out a frame of data if any is in the transmit regist er, whereas if the signal is de asserted, the data will be held in the transmit register. the signal is checked at the beginning of eac h frame of transmit data. the enrx1_n is the enable - receiver - request for asynchronous serial port 1 when the enrx1 bit (b it [ 6 ] ) in the auxiliary control register (auxcon) is 1 and hardware flow control is enabled for this port (fc bit [b it ( 9 )] in the ser ial port 1 control register [sp1ct] ) . this signal enables the receiver of asynchronous serial port 1. 2.2.29 pcs3_n/rts1_n/rtr1_n/pio18 peripheral chip select 3 (synchronous output)/ ready - to - send 1 (asynchronous output)/ ready - to - receive 1 (asynchronous input) th e pcs3_n signal provides an indication that a memory access is under way for the fourth region of the peripheral memory block (i/o or memory address space). the base address of the peripheral memory block is programmable. the pcs3_n is held high during b oth bus hold and reset. this output is asserted with the ad address bus over a 256 - byte range. the rts1 - n is the ready - to - s end signal for asynchronous serial port 1 when the rts1 bit (b it [ 5 ] ) in the auxiliary control register (auxcon) is 1 and hardware f low control is enabled for this port (fc bit [b it ( 9 )] in the serial port 1 control register [sp1ct] ) . this signal is asserted when the serial port transmit register contains untransmitted data. the rtr1 - n is the ready - to - r eceive signal for asynchronous serial port 1 when the rts1 bit (b it [ 5 ] ) in the auxiliary control register (auxcon) is 0 and hardware flow control is enabled for this port (fc bit [b it ( 9 )] in the serial port 1 control register [sp1ct] ) . this signal is asserted when the serial port re ceive register does not contain valid, unread data. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 40 of 154 1 - 888 - 824 - 4184 2.2.30 pcs5_n/a1/pio3 peripheral chip select 5 (synchronous output)/ latched address bit [ 1 ] (synchronous output) the pcs5_n signal provides an indication that a memory access is under way for the sixth region of the peripheral memory block (i/o or memory address space). the base address of the peripheral memory block is programmable. the pcs5_n is held high during both bus hold and reset. this output is asserted with the ad address bus over a 256 - byte range. th e a1 pin provides and internally latched address b it [ 1 ] to the system when the ex bit (b it [ 7 ] ) in the mcs_n and pcs_n auxiliary (mpcs) register is 0. it retains its previously latched value during a bus hold. 2.2.31 pcs6_n/a2/pio2 peripheral chip select 6 ( synch ronous output)/latched address b it [ 2 ] (synchronous output) th e pcs6_n signal provides an indicatio n that a memory access is under way for the seventh region of the peripheral memory block (i/o or memory address space). the base address of the periphe ral memory block is programmable. the pcs6_n is held high during both bus hold and reset. this output is asserted with the ad address bus over a 256 - byte range. th e a2 pin provides an internally latched address b it [ 2 ] to the system when the ex bit (b it [ 7 ] ) in the mpcs register is 0. it retains its previously latched value during a bus hold. 2.2.32 pio3 1 C pio0 programmable i/o pins (asynchronous input/output open - drain) there are 32 individually pio pins provided. 2.2.33 rd_n read strobe (synchronous output with trist ate) this pin provides an indication to the system that a me mory or i/o read cycle is under way. it will not to be asserted before the ad bus is floated during the address to data transition. the rd_n is tristated during bus hold. 2.2.34 res_n reset (asynchronou s level - sensitive input) this pin forces a reset on the microcontroller. it has a schmitt trigger to allow por generation via an rc network. when this signal is asserted, the microcontroller immediately terminates its present activity, clears its interna l logic, and transfers cpu control to the reset address, ffff0h. the res_n must be asserted for at least 1 ms and may be asserted asynchronously to clkouta as it is synchron ized internally. furthermore, v cc must be within specification and clkouta must be stable for more than four of its clock periods for the period that res_n is asserted. the microcontroller starts to fetch instructions 6.5 clkouta clock periods after the deassertion of res_n . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 41 of 154 1 - 888 - 824 - 4184 2.2.35 rfsh2_n/aden_n ( ia188es only ) refresh 2 (sy nchronous outpu t with tristate) /address enable (input with internal pullup) the rfsh2_n i ndicates that a dram refresh cycle is being performed when it is asserted low. however, this is not valid in psram mode where mcs3_n/rfsh_n is used instead. if aden_n is held high d uring por , the ad bus ( ao15 C ao8 and ad7 C ad0 ) is controlled during the address portion of the lcs and ucs bus cycles by the da bit (b it [ 7 ] ) in the lmcs and umcs registers. if the da bit is 1, the address is accessed on the a19 C a0 pins reducing power consu mption. the weak pullup on this pin obviates the necessity of an external pullup. if this pin is held low during por , the ad bus is used for both addresses and data without regard for the setting of the da bits. the rfsh2_n/aden_n is sampled one crystal clock cycle after the rising edge of res_n and is tristated during bus holds and once mode. 2.2.36 rts0_n/rtr0_n/pio20 ready - to - send 0 (asynchronous output)/ready - to - receive 0 (asynchronous input) the rts0 - n is the ready - to - s end signal for asynchronous serial p ort 0 when the rts0 bit (b it [ 3 ] ) in the auxiliary control register (auxcon) is 1 and hardware flow control is enabled for this port (fc bit [b it ( 9 )] in the serial port 1 control register [sp1ct] ) . this signal is asserted when the serial port transmit re gister contains untransmitted data. the rtr0 - n is the ready - to - r eceive signal for asynchronous serial port 0 when the rts0 bit (b it [ 3 ] ) in the auxiliary control register (auxcon) is 0 and hardware flow control is enabled for this port (fc bit [b it ( 9 )] in the serial port 1 control register [sp1ct] ) . this signal is asserted when the serial port receive register does not contain valid unread data. 2.2.37 r xd0_n/pio23 receive data 0 (asynchronous input) this signal connects asynchronous serial receive data from the system to the asynchr onous serial port 0. 2.2.38 rxd1_n/pio28 receive data 1 (asynchronous input) this signal connects asynchronous serial receive data from the system to the asynchronous serial port 1. 2.2.39 s2_n C s0_n bus cycle status (synchronous outputs with tristate) these three signals inform the system of the type of bus cycle is in progress. the s2_n may be used to indicate whether the current access is to memory or i/o, and s1_n may be used to indicate whether data is being transmitted or received. thes e signals are tristated during bus hold and hold acknowledge. the coding for these pins is presented in t able 10 . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 42 of 154 1 - 888 - 824 - 4184 table 10 . bus cycle types for s2_n, s1_n, and s0_n s2_n s1_n s0_n bus cycle 0 0 0 interrupt acknowledge 0 0 1 re ad data from i/o 0 1 0 write data to i/o 0 1 1 halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 none (passive) 2.2.40 s6/lock_n/clkdiv2_n/pio29 bus cycle stat us b it [ 6 ] (synchronous output)/bus lock (synchronous ou tput)/ clock divide by 2 (input with internal pullup) th e s6 signal is high during the seco nd and remaining cycle periods ( i.e. , t 2 C t 4 ) , indicating that a dma - initiated bus cycle is under way. the s6 is tristated during bus hold or reset. th e lock_n signa l is held low to indicate to other system bus masters that the system bus is being used and that no attempt should be made to try to gain control of it. this signal is only available during t 1 and is intended for emulator use. the microcontroller enters c lock divide - by - 2 mode, if clkdiv2_n is held low during power - on - reset. in this mode, the pll is disabled and the processor receive s the external clock divided by 2. sampling of this pin occurs on the rising edge of res_n . should this pin be used as pio29 configured as an input, care should be taken that it is not driven low during power - on - reset. this pin has an internal pullup so it is not necessary to drive the pin high even though it defaults to an input pio. 2.2.41 srdy/pio6 synchronous ready (synchronous l evel - sensitive input) this signal is an active high input synchronized to clkouta and indicates to the microcontroller that a data transfer will be completed by the addressed memory space or i/o device. in contrast to the asynchronous ready ( ardy ), which requires internal synchronization, srdy permits easier system timing as it already synchronized. tying srdy high will always assert this ready condition, whereas tying it low will give control to ardy . 2.2.42 tmrin0/pio11 timer input 0 (synchronous edge - sensit ive input) this signal may be either a clock or control signal for the internal timer 0. the timer is incremented by the microcontroller after it synchronizes a rising edge of tmrin0 . when not used, tmrin0 must be tied high, or when used as pio11 it is p ulled up internally. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 43 of 154 1 - 888 - 824 - 4184 when pulse width demodulation mode is enabled, tmrin0 is driven internally by int2/inta0_n/pwd allowing for the pin to be configured as pio11 . 2.2.43 tmrin1/pio0 timer input 1 (synchronous edge - sensitive input) this signal may be either a cl ock or control signal for the internal timer 1. the timer is incremented by the microcontroller after it synchronizes a rising edge of tmrin1 . when not used, tmrin1 must be tied high. when used as pio0 , it is pulled up internally. when pulse width demo dulation mode is enabled, tmrin1 is driven internally by int2/inta0_n/pwd , allowing for the pin to be configured as pio0 . 2.2.44 tmrout0/pio10 timer output 0 (synchronous output) this signal provides the system with a single pulse or a continuous waveform with a programmable duty cycle. it is tristated during a bus hold or reset. 2.2.45 tmrout1/pio1 timer output 1 (synchronous output) this signal provides the system with a single pulse or a continuous waveform with a programmable duty cycle. it is tristated during a b us hold or reset. 2.2.46 txd0/pio22 transmit data 0 (asynchronous output) this pin provides the system with asynchronous serial transmit data from serial port 0. 2.2.47 txd1/pio27 transmit data 1 (asynchronous output) this pin provides the system with asynchronous seria l transmit data from serial port 1. 2.2.48 ucs_n/once 1_n upper memory chi p select (synchronous output)/ once mode request 1 (input with internal pullup) th e ucs_n pin provides an indication that a memory access is in progress to the upper memory block. the size o f the upper memory block and its base address are programmable, with the size adjustable up to 512 kbytes. the ucs_n is held high during bus hold. after reset , ucs_n is active for the 64 - kbyte memory range from f0000h to fffffh, which includes the reset a ddress at ffff0h. the once1_n pin ( on c ircuit e mulation ) and its companion pin , once0_n , define the microcontroller mode during reset. these two pins are sampled on the rising edge of res_n and if both are asserted low, the microcontroller starts in once mode, o therwise it starts normally. in once mode, all pins are tristated and remain so until a subsequent reset. to prevent the microcontroller from entering once mode inadvertently, this pin has a weak pullup that is only present during reset. t his pin is not tristated during bus hold. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 44 of 154 1 - 888 - 824 - 4184 2.2.49 uzi_n/pio26 upper zero indicate (synchronous output) this pin allows the designer to determine if an access to the interrupt vector table is in pr ogress by oring it with bits [ 15 C 10 ] of the address and data bus ( ad15 C ad10 on the ai186 and ao1 5 C ao10 on the ia 188 es ). the uzi_n is the logical and of the inverted a19 C a16 bits. it asserts in the first period of a bus cycle and is held throughout the cycle. 2.2.50 v cc power supply (input) these pins supply power (+5v + 10% ) to the mic rocontroller. 2.2.51 whb_n ( ia186es only ) write hi gh byte (synchronous output with tristate) this pin and wlb_n provide an indication to the system of which bytes of the data bus (upper, lower, or both) are taking part in a write cycle. the whb_n is asserted wit h ad15 C ad8 and is the logical or of bhe_n and wr_n . it is tristated during reset. 2.2.52 wlb_n/wb_n write low byte ( ia186es only ) (sy nchronous output with tristate) /write byte ( ia188 es only ) (synchronous output with tristate) the wlb_n and whb_n provide an indic ation to the system of which bytes of the data bus (upper, lower, or both) are taking part in a write cycle. the wlb_n is asserted with ad7 C ad0 and is the logical or of ad0 and wr_n . it is tristated during reset. on the ia188es microcontroller, wb_n prov ides an indication that a write to the bus is occurring. it shares the same early timing as that of the non - multiplexed address bus, and is associated with ad7 C ad0. it is tristated during reset. 2.2.53 wr_n write strobe (synchronous output) this pin provides an indication to the system that the data currently on the bus is to be written to a memory or i/o device. it is tristated during a bus hold or reset. 2.2.54 x1 crystal input this pin and x2 are the connections for a fundamental mode or third - overtone, parallel - re sonant crystal used by the internal oscillator circuit. an external clock source for the microcontroller is connected to x1 while the x2 pin is left unconnected. 2.2.55 x2 crystal input this pin and x1 are the connections for a fundamental mode or third - overtone , parallel - resonant crystal used by the internal oscillator circuit. an external clock source for the microcontroller is connected to x1 while the x2 pin is left unconnected. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 45 of 154 1 - 888 - 824 - 4184 2.3 pins used by emulators the following pins are used by emulators: a19 C a0 ao15 C a o8 ad7 C ad0 ale bhe_n aden_n (on the ia186es ) clkouta rfsh2_n/aden_n (on the ia 188 es ) rd_n s2_n C s0_n s6/lock_n/clkdiv2_n uzi_n emulators require that s6/lock_n/clkdiv2_n and uzi_n be config ured as their normal functions ( i.e. , as s6 and uzi_n , respectively ) . holding bhe_n/aden_n ( ia 186 es ) or rfsh_n/aden_n ( ia188es ) low during the rising edge of res_n, s6 , and uzi_n will be configured at reset in their norm al functions instead of as pios . 3. maximum ratings, thermal characteristics, and dc parameters for the i nnovasic semiconductor ia186es and ia188es microcontrollers, the absolute maximum ratings, thermal characteristics, and dc parameters are provided in tables 11 through 1 3 , respectively. table 11 . ia186es and ia188es absolute maxim um ratings parameter rating storage temperature ?65c to +125 c voltage on any pin with respect to v ss ?0.5v to +( v cc + 0.5)v table 12 . ia186es and ia188es thermal characteristics symbol characteristic value t a ambient temperature - 40 c to 85 c ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 46 of 154 1 - 888 - 824 - 4184 table 13 . dc characteristics over commercial operating ranges symbol parameter description test conditions preliminary unit min max v il input low voltage (except x1 ) C ? 0.5 0.8 v v il1 clock input low voltage ( x1 ) C ? 0.5 0.8 v v ih input high voltage (except res_n and x1 ) C 2.0 v cc +0.5 v v ih1 input high voltage (res_n) C 2.4 v cc +0.5 v v ih2 clock input high voltage ( x1 ) C v cc C 0.8 v cc +0.5 v v ol output low voltages i ol = 2.5 ma (s2_n C s0_n) C 0.45 v i ol = 2.0 ma (other) C 0.45 v v oh output high v oltages a i oh = ? 2.4 ma @ 2.4 v 2.4 v cc + 0.5 v i oh = ? 200 a @ v cc ? 0.5 v cc ? 0.5 v cc v i cc power supply current @ 0 c v cc = 5.5 v b C 5.9 ma/ mhz i li input leakage current @ 0.5 mhz 0.45 v v in v cc C 10 a i lo output leakage current @ 0.5 mhz 0.45 v v out v cc c C 10 a v clo clock output low i clo = 4.0 ma C 0.45 v v cho clock output high i cho = ? 500 a v cc ? 0.5 C v a the lcs_n/once0_n , mcs3_n C mcs0_n , ucs_n/once1_n , and rd_n pins have weak internal pullup resistors. loading the lcs_n/once0_n and ucs_n/once1_n pins in excess of i oh = ? 200 a during reset can cause the device to go into once mode. b current is measured with the device in reset with the x1 and x2 driven and all other non - power pins open but held high or low . c testing is performed with the pins flo ating, either during hold or by invoking the once mode. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 47 of 154 1 - 888 - 824 - 4184 4. device architecture a functional block diagram of the ia186es/ia188es is shown in figure 7 . this microcontroller consists of t he following functional blocks. bus interface and control (bic) chip s elects and control (csc) programmable i/o clock and power management dma interrupt controller timers asynchronous serial ports (2). 4.1 bus interface and control the bic manages all accesses to external memory and external peripherals. these peripherals may b e mapped either in memory space or i/o space. the bic supports both multiplexed and non - multiplexed bus operations. multiplexed address and data are provided on the ad [15 C 0] bus, while a non - multiplexed a ddress is provided on the a [19 C 0] bus. the a bu s provides address information for the entire bus cycle (t 1 C t 4 ), while the ad bus provides address information only during the first (t 1 ) phase of the bus cycle. for details regarding bus cycles, see chapter 6 , ac spec ifications . the bic provide the capability to dynamically alter the size of the data bus. by programming the auxiliary control register (auxcon), a user may easily support external peripherals and memory devices of both 8 - and 16 - bit widths without speci alized micro - code managing the data accesses. the auxcon register contains 3 programmable bits for this purpose: lsiz , msiz , and iosiz . for details regarding the operation of these bits, see section 5.1, control an d registers . the ia186es microcontroller provides two signals to support this functionality, write high byte ( whb_n ) and write low byte ( wlb_n ). t he ia188es microcontroller requires only a single write byte ( wb_n ) signal to support its 8 - bit data bus. the bic also provides support for psram devices. psram is supported in the lower chip select ( lcs_n ) area only. in order to support psram , the csc must be appropriately programmed. for details regarding this operation , see section 4.7, chips selects . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 48 of 154 1 - 888 - 824 - 4184 figure 7 . functional block diagram note: see pin descriptions for pins that share other functions with pio pins. pins pwd, int5, int6, rts1_n/rtr1_n, and cts1_n/enrx1_n are multiplexed with int 2_n/inta0_n, drq0, drq0, pcs3_n, and pcs2_n , respectively. ? b u s i n t e r f a c e a n d c o n t r o l ( ) u z i _ n s 6 / l o c k _ n / c l k d i v 2 _ n h o l d h l d a s r d y d e n _ n / d s _ n a r d y d t r _ n s 2 _ n C s 0 _ n p e r i p h e r a l c o n t r o l a n d r e g i s t e r s c h i p s e l e c t s a n d c o n t r o l p r o g r a m m a b l e i / o r d _ n w h b _ n w l b _ n w r _ n a l e b h e _ n / a d e n _ n a [ 1 9 : 0 ] a d [ 1 5 : 0 ] l c s _ n / o n c e 0 _ n m c s 3 _ n / r f s h _ n u c s _ n / o n c e 1 _ n p c s 5 _ n / a 1 p c s 6 _ n / a 2 p c s 3 _ n C p c s 0 _ n m c s 2 _ n C m c s 0 _ n p i o [ 3 1 : 0 ] c l o c k a n d p o w e r m a n a g e m e n t d i r e c t m e m o r y a c c e s s i n t e r r u p t c o n t r o l l e r p u l s e w i d t h d e m o d u l a t o r ( p w d ) t i m e r s a s y n c h r o n o u s s e r i a l p o r t 0 a s y n c h r o n o u s s e r i a l p o r t 1 i n s t r u c t i o n d e c o d e a n d e x e c u t i o n d r q 0 / i n t 5 d r q 1 / i n t 6 c l k o u t a c l k o u t b v c c g n d i n t 4 i n t 3 / i n t a 1 _ n i n t 2 / i n t a 0 _ n i n t 1 / s e l e c t _ n i n t 0 n m i p w d t m r i n 0 t m r o u t 0 t m r i n 1 t m r o u t 1 t x d 0 r x d 0 c t s 0 _ n / e n r x 0 _ n r t s 0 _ n / r t r 0 _ n t x d 1 r x d 1 c t s 1 _ n / e n r x 1 _ n r t s 1 _ n / r t r 1 _ n r e s _ n ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 49 of 154 1 - 888 - 824 - 4184 4.2 clock and power management a phase - lock - loop (pll) and a second programmable system clock output ( clkoutb ) are included in the clock and power management unit. the internal clock is the same freq uency as the crysta l but with a duty cycle of 45% to 55%, as a worst case, generated by the pll obviating the need for a 2x external clock. a por resets the pll (see figure 8). figure 8 . crystal configuration 4.3 system clocks if r equired , the internal oscillator may be driven by an external clock source that should be connected to x1 , leaving x2 unconnected. the clock outputs , clkouta and clkoutb , may be enabled or disabled individually ( syscon register bits [ 11 C 8 ] ). these clock c ontrol bits allow one clock output to run at pll frequency and the other to run at the power - save frequency (see figure 9) . figure 9 . organization of clock ? c r y s t a l x 1 i a 1 8 6 e s / i a 1 8 8 e s x 2 c 2 c 1 r e c o m m e n d e d r a n g e o f v a l u e s f o r c 1 a n d c 2 a r e : c 1 = 1 5 p f 2 0 % c 2 = 2 2 p f 2 0 % x 1 , x 2 p l l p o w e r - s a v e d i v i s o r ( / 2 t o / 1 2 8 ) m u x m u x t i m e d e l a y 6 2 . 5 n s d r i v e e n a b l e c l k o u t a c l k o u t b d r i v e e n a b l e p r o c e s s o r i n t e r n a l c l o c k ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 50 of 154 1 - 888 - 824 - 4184 4.4 power - save mode the operation of the cpu and peripheral operate at a sl ower clock frequency when in power save mode , reducing power consumption and thermal dissipation. should an interrupt occur, the microcontroller returns to its normal operating frequency automatically on the internal clocks next rising edge in t 3 . any c lock - depende nt devices should be reprogrammed for the cha nge in frequency during the power - save mode period. 4.5 initialization and reset the res_n (reset), the highest priority interrupt, must be held low for 1 m s during power - up to initialize the microcontro ller correctly. this operation makes the device cease all instruction execution and local bus activity. the microcontoller begins instruction execution at physical address ffff0h when res_n becomes inactive and after an internal processing interval with ucs_n is asserted and three wait states. reset also sets up certain registers to predetermined values and resets the wdt . 4.6 reset configuration register the data on the address/data bus ( ad15 C ad0 for the ia 186es and ao15 C ao8 and ad7 C ad0 for the ia 188es) are written into the reset configuration register when reset is l ow. this data is system - depende nt and is held in the reset configuration register after reset is de - asserted. this configuration data may be placed on the address/data bus by using weak extern al pull - up and pull - down resistors or applied to the bus by an external driver, as the processor does not drive the bus during reset. it is a method of supplying the software with s ome initial data after a reset (e.g., option jumper positions ) . 4.7 chip selec ts chip - select generation is programmable for memories and peripherals. programming is also available to produce ready and wait - state generation plus latched address bits a1 and a2 . for all memory and i/o cycles, the chip - select lines are active within t heir programmed areas, regardless of whether they are generated by the internal dma unit or the cpu. there are six chip - select outputs for memory and a further six for peripherals whether in memory or i/o space. the memory chip - selects are able to address three memory ranges, whereas the peripheral chip - selects are used to address 256 - byte blocks that are offset from a programmable base address. writing to a chip - select register enables the related logic even in the event that the pin in question has anot her function (e.g., where a pin is programmed to be a pio ) . 4.8 chip - select timing for normal timing, the ucs_n and lcs_n outputs are asserted with the non - multiplexed address bus. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 51 of 154 1 - 888 - 824 - 4184 4.9 ready - and wait - state programming each of the memory or peripheral chip - select lines can have a ready signal programmed that can be the ardy or srdy signal. the chip - select control registers (umcs, lmcs, mmcs, pacs, and mpcs) have a single bit that selects if the external ready signal is to be used or not ( r2 , b it [ 2 ] ). r1 and r0 ( bits [ 1 C 0 ] ) in these registers control the number of wait states that are inserted during each access to a memory or peripheral location (from 0 to 3). the control registers for pcs3_n C pcs0_n use three bits, r3, r1 C r0 ( bit [ 3 ] and bits [ 1 C 0 ] ) to provide 5 , 7, 9, and 15 wait states in additio n to the original values of 0 C 3 wait states. w he n an external ready has been selected as required, internally programmed wait states will always be completed before the external ready can finish or extend a bus cycle. c onsider a sys tem in which the number of wait states to be inserted has been set to three. t he external ready pin is sampled by the processor during the first wait cycle. if the ready is asserted, the access is completed after seven cycles (4 cycles plus 3 wait cycles) . i f the ready is not asserted , during the first wait cycle the access is prolonged until read y is asserted and two more wait states are inserted followed by t 4. the ardy signal is an asynchronous ready with a pin that is active high and a ccepts a rising edge asynchronous to clkouta . however, an additional clock period may be necessary if the falling edge of ardy is not synchronized to clkouta . 4.10 chip - select overlap overlapping chip selects are those configurati ons in which more than one chi p select is asserted for the same physical address. if pcs is configured in i/o space with lcs or any other chip select configured for memory, address 00000h is not overlapping the chip selects. it is not recommended that multiple chip - select signals be a sserted for the same physical address, although it may be unavoidable in certain systems. if this is the case, all overlapping chip select s must have the same external ready configuration and the same number of wait states to be inserted into access cycle s. internal signals are employed to access the peripheral control block (pcb). these signals serve as chip selects t hat are configured with no wait states and no external ready. only when these chip selects are configured in the same manner can the pcb b e programmed with addresses that overlap external chip select s. care should be exercised in the use of the da bit in the lmcs or umcs registers when overlapping an additional chip select with either the lcs_n or ucs_n chip select s. setting the da bit to 1 prevents the address from being driven onto the ad bus for all accesses for which the respective chip select is active, including those for which the multiple selects are active. the mcs_n and pcs_n pins are dual - purpose pins, either as chip select s or pio inputs or outputs. however, their respective ready - and wait - state configurations for their chip - select function will be in effect regardless of the function for which they are actually programmed. their ready - and ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 52 of 154 1 - 888 - 824 - 4184 wait - state settings must agree with those for any overlapping chip selects as though they had been configured as chip selects . this is true regardless of whether these pins are configured as pio and enabled (by writing to the mmcs and mpcs registers for the mcs_n chip select s and to the pa cs and mpcs registers for the pcs_n chip select s). even though pcs4_n is not available as an external pin , it has ready - and wait - state logic and must therefore follow the rules for overlapping chip select s. by contrast, the pcs6_n and pcs5_n have ready a nd wait - state l ogic that is disabled when they are configured as address bits a2 and a1 , respectively. if the chip - select - configuration rules are not followed , the processor may hang with the appearanc e of waiting for a ready signal even in a system where ready ( ardy or srdy ) is always set to 1. 4.11 uppe r - memory chip select the ucs_n chip select is for the top of memory. on reset , the micro controller begins fetching and executing instructions at memory location ffff0h, so upper memory is usually use d for ins truction. to this end , ucs_n is active on reset and has a memory range of 64 kbytes (f0000h to fffffh) as default , along with external ready required and three wait state s automatically inserted. the lower boundary of ucs_n is programmable to provide ran ges of 64 to 512 kbytes. 4.12 low - memory chip select the lcs_n chip select is for lower memory and may be configured for 8 - or 16 - bit accesses by the auxcon register. because the interrupt vector table is at the bottom of memory beginning at 00000h, this pin i s usually use d for control data memory. unlike ucs_n , this pin is inactive on reset. 4.13 midrange - memory chip selects there are four midrange chip select s, mcs3_n C mcs0_n , which may be used in a user - located memory block. with some exceptions, the base addres s of the memory block may be located anywhere in the 1 - mbyte memory address space. the memory spaces used by the ucs_n and lcs_n chip select s are excluded, as are pcs6_n, pcs5_n, and pcs3_n C pcs0_n . if the pcs_n chip select s are mapped to i/o space , the m cs address range can overlap the pcs address range. the mcs0_n chip select may be programmed to be active over the entire mcs range , leaving the mcs3_n C mcs1_n free for use as pio pins. the mcs may be configured for 8 - or 16 - bit acc esses by the auxcon regis ter. the width of the non - ucs/non - lcs memory ranges determines the mcs range bus width. the assertion of the mcs outputs occurs with the same timing as the multiplexed ad address bus. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 53 of 154 1 - 888 - 824 - 4184 4.14 peripheral chip selects there are six peripheral chip select s, pcs6_n, pcs5_n, and pcs3_n C pcs0_n , which may be used within a user - defined memory or i/o block. except for the spaces associated with the ucs_n , lcs_n , and mcs_n chip selects, the base address can be located any where within the 1 - mbyte memory - address space or pr ogrammed to the 64 - kbyte i/o space. the pcs4_n is not available. none of the pcs_n pins are active at reset. the pcs6_n C pcs5_n and pcs3_n C pcs0_n may be programmed to have 0 to 3 wait state s. the pcs3_n C pcs0_n may be also programmed to have 5, 7, 9, and 15 wait state s. the pcs may be configured for 8 - or 16 - bit accesses by the auxcon register. the pcs range bus width is determined either by that of the non - ucs/non - lcs memory range or by the width of the i/o space. the assertion of the pcs outputs occurs with the same timing as the multiplexed ad address bus. each of the pcs operates over a 256 - byte address range. 4.15 refresh control the refresh control unit (rcu) automatically generates refresh bus cycles with a fixed wait - state value of three for the psram automatic refresh mo de. the rcu generates a memory - read request after a programmable period of time to the bus interface unit. the ena bit in the enable rcu register (edram) enables refresh cycles, operating off the processor internal clock. if the proc essor is in power - save mode, the rcu must be reconfigured for the new clock rate. if the hlda pin is asserted when a refresh request is initiated (indicating a bus - hold condition), the processor disables the hlda pin to allow a refresh cycle to be performe d. the external circuit bus master must deassert the hold signal for at least one clock period to permit the execution of the refresh cycle. 4.16 interrupt control interrupt requests originate from a variety of internal and external sources that are arranged i n priority order by the internal interrupt controller and are presented sequentially to the processor. ei ght external - interrupt sources are connected to the processor. these include seven maskable and one nonmaskable interrupt (nmi). eight internal - int errupt sources are also connected to the processor. these include those not brought out to external pins three timers, two dma channels, two asynchronous serial ports, and the wdt nmi. interrupts int6 and int5 ( multiplexed with drq1 and drq0 ) are availab le if the respective dma is not enabled or is internally synchronized. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 54 of 154 1 - 888 - 824 - 4184 with the exception of int0 , the seven external maska ble interrupt request pins are multifunction al . on e function is for direct - interrupt requests. the int6 and int5 are edge - triggered . the int4 C int0 may be either level - or edge - triggered. when configured in cascade mode, int1 and int0 interface with an external 82c59a - type interrupt controller. when int0 is configured for cascade mode, the function of int2 is automatically switched t o its inta0_n role. similarly , when int1 is configured for cascade mode , int3 is switched to its inta1_n role. an external 82c59a - compatible interrupt controller may be used as the system master by programming the internal interrupt controller to slave m ode, but int6 C int4 cannot be used. although other interrupts are disabled when another is accepted, these may be re - enabled by setting the interrupt enable flag ( if ) in the processor status flags register during the interrupt service routine (isr). settin g if permits interrupts of equal or greater priority to interrupt the currently running isr. further interrupts from the same source will be blocked until the corresponding bit in the in - service (inserv) register is cleared. when set to 1, the special f ully nested mode ( sfnm ) is invoked for int0 and int1 in the int0 and int1 control registers, respectively. in this mode , a new interrupt may be generated by these sources regardless of the in - service bit. the following table shows the priorities of the i nterrupts at por . 4.17 interrupt types table 14 presents interrupt names, types, vector table address, end - of - interrupt ( eoi ) type, overall priority, and related instructions. table 14 . interrupt types interrupt name interrupt type vec tor table address eoi type overall priority related instructions divide error exception a 00h 00h na 1 div, idiv trace interrupt b 01h 04h na 1a all non - maskable interrupt (nmi) 02h 08h na 1b C breakpoint interrupt a 03h 0ch na 1 int3 int0 detected overf low exception b 04h 10h na 1 int0 array bounds exception a 05h 14h na 1 bound unused opcode exception a 06h 18h na 1 undefined opcodes esc opcode exception a ,b 07h 1ch na 1 esc opcodes timer0 interrupt d,e 08h 20h 08h 2a C timer1 interrupt d,e 12h 48h 08h 2 b C ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 55 of 154 1 - 888 - 824 - 4184 table 14. interrupt types (continued) interrupt name interrupt type vector table address eoi type overall priority related instructions timer2 interrupt d,e 13h 4ch 08h 2c C reserved 09h 24h C C C dma 0 interrupt/int5 e 0ah 28h 0ah 3 C dma1 interru pt/int6 e 0bh 2ch 0bh 4 C int0 interrupt 0ch 30h 0ch 5 C int1 interrupt 0dh 34h 0dh 6 C int2 interrupt 0eh 38h 0eh 7 C int3 interrupt 0fh 3ch 0fh 8 C int4 interrupt f 10h 40h 10h 9 C asynchronous serial port 1 interface f 11h 44h 11h 9 C asynchronous s erial port 0 interface f 14h 50h 14h 9 C reserved 15h C 1fh 54h C 7ch C C C note : if the priority levels are not changed , the default priority level will be used for the interrupt sources. a instruction execution generates interrupts. b performed in the same m anner as for the 8086 and 8088. c an esc opcode causes a trap. d because o nly one irq is generated for the three timers, they share priority level with other sources. the timers have an interrupt priority order among themselves (2a > 2b > 2c). e these interr upt types are programmable in slave mode. f not available in slave mode. 4.18 timer control the ia186es and ia188es have a wdt and three 16 - bit programmable timers. timer0 and timer1 each has an input and output connected to external pins that permit s it to cou nt or time events as well as produce variable duty - cycle waveforms or non - repetitive waveforms. these same timers are used to measure the high - and low - pulse widths of the pulse width demodulator on the pwd pin. because timer2 does not have external conne ctions, it is confine d to internal functions such as real - time coding, time - delay applications, a prescaler for timer0 and timer1, or to synchronize dma transfers. the peripheral control block contains eleven 16 - bit registers to control the programmable ti mers. each timer - count register holds the present value of its associated timer and may be read from or written to whether the timer is in operation or not. the microcontroller increments the value of the timer - count register when a timer event takes pla ce. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 56 of 154 1 - 888 - 824 - 4184 the value stored in a timers associated maximum count register determines its maximum count value . upon reaching it, the timer count register is reset to 0 in the same clock cycle that this count was attained . t he timer count register does not stor e this maximum value. both timer0 and timer1 have a primary and a secondary maximum count register that permits each to alternate between two discrete maximum values. timer0 and timer1 may have the maximum count registers configured in either primary only or both primary and secondary. if the primary only is configured to operate , on reaching the maximum count , the output pin will go low for one clock period. if both the primary and secondary registers are enabled, the output pin reflects the state of th e register in control at the time . this generates the required waveform that is dependent on the two values in the maximum count registers. because they are polled every fourth clock period, the timers can operate at a quarter of the internal clock freque ncy. although an external clock may be used , the timer output may take six clock cycles to respond to the input. 4.19 watchdog timer the wdt operates in real wdt fashion and may be used to prevent loss of control in the event that software does not respond in an expected manner. the wdt is active after reset, has a maximum timeout count, and is prog rammed for system reset mode. the wdt control register (wdtcon) may be written to only once after reset. this is accomplished by writing 3333h, then cccch followe d by the new configuration data to the wdtcon register. provided they do not include access to the wdtcon register, any number of operations may be performed between these two words , including memory and i/o reads and writes . writing aaaah then 5555h to the wdtcon register resets the current count. this count cannot be read. provided they do not include access to the wdtcon register, any number of operations may be performed between these two words, including memory and i/o reads and writes. u se of th ese sequences is intend ed to prevent executing code from block ing a wdt event. with the wdt, a maximum 1.67 - second timeout period is possible in a 40 - mhz system . the wdt can be programmed to generate either an nmi or a system reset when it times out. if programmed to generate an nmi, the nmiflag (b it [ 12 ] ) in the wdtcon register will be set when it occurs. this flag should be tested by the nmi interrupt service routine (isr) to establish whether the wdt or an external source generated the interrupt. if set by writing the 3333h and cccch sequence followed by the configuration data that includes clearing nmiflag , the isr should clear this flag . if the nmiflag is set while a second wdt timeout occurs , a wdt system reset is generated in place of a second nm i interrupt . the rstflag (b it [ 13 ] ) in the wdtcon register is set if a wdt reset is generated, due to one wdt occurrence while the wdt is programmed to generate resets, or because a wdt event ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 57 of 154 1 - 888 - 824 - 4184 occurred with the nmiflag set. this permits system initializati on code to distinguish between a wdt reset and hardware reset and take appropriate action. the rstflag is cleared by a read or write to the wdtcon register. during a wdt reset, the external pins are not re - sampled, ensuring that clocking, reset configura tion register, and any other features that are user programmable during reset do not change when a wdt system reset occurs. all other activities are the same as those of a normal system reset. 4.20 direct memory access dma frees the cpu from involvement in tra nsferring data between memory and peripherals over either one or both high - speed dma channels. data may be transferred from memory to i/o, i/o to memory, memory to memory, or i/o to i/o. dma channels may be connected to asynchronous serial ports. the i a186es microcontroller supports the t ransfer of both bytes and words to and from even or odd addresses . i t does not support word transfers to memory that is configured for byte accesses. the ia188es does not support word transfers at all. each data tran sfer will take two bus cycles (a minimum of 8 clock cycles). there are four sources of dma request s for both dma channels: the channel request pin ( drq1 C drq0 ) timer2 a serial port the system software. each channel may be programmed to have a different prio rity either to resolve a simultaneous dma request or to interrupt a transfer on the other channel. 4.21 dma operation the pcb contains six registers for each dma channel to control and speci fy the operation of the channel (see figure 10) : two registers to stor e a 20 - bit source address two registers to stor e a 20 - bit destination address one 16 - bit transfer - count register one 16 - bit control register the number of dma transfers required is designated in the dma transfer count register and may contain up to 64 k by tes or words . it will end automatically. dma channel function is defined by the control registers . like the other five registers, these may be changed at any time ( including during a dma transfer ) and are implemented immediately. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 58 of 154 1 - 888 - 824 - 4184 figure 10 . dma unit 4.22 dma channel control registers see section 5.1.10, d1con (0dah) and d0con (0cah) . t he dma channel control registers specify the following: whether the data destination is in memory or i/o space ( bit [15]) whether the destination address is incremented, decremented, or unchanged after each transfer (bits [14 C 13]) whether the data source is in memory or i/o space (bit [12]) whether the source address is incremented, decremented, or unchanged after e ach transfer (bits [11 C 10]) ? d r q 1 2 0 - b i t a d d e r / s u b t r a c t o r 2 0 t r a n s f e r c o u n t e r c h . 1 d e s t i n a t i o n a d d r e s s c h . 1 s o u r c e a d d r e s s c h . 1 t r a n s f e r c o u n t e r c h . 0 d e s t i n a t i o n a d d r e s s c h . 0 s o u r c e a d d r e s s c h . 0 a d d e r c o n t r o l l o g i c d m a c o n t r o l l o g i c t i m e r r e q u e s t r e q u e s t s e l e c t i o n l o g i c i n t e r r u p t r e q u e s t d r q 0 2 0 c h a n n e l c o n t r o l r e g i s t e r 1 c h a n n e l c o n t r o l r e g i s t e r 0 1 6 i n t e r n a l a d d r e s s / d a t a b u s ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 59 of 154 1 - 888 - 824 - 4184 whether dma transfers cease upon reaching a designated count (bit [9]) whether the last transfer generates an interrupt (bit [8]) synchronization mode (bits [7 C 6]) the relative priority of one dma channel with respect to the oth er (bit [5]) acceptance of dma requests from timer2 (bit [4]) configuration of drq pins as int (bit [3]) byte or word transfers (bit [0]) 4.23 dma priority with the exception of word accesses to odd memory locations or between locked memory addresses, dma trans fers have a higher priority than cpu transfers. because the cpu cannot access memory during a dma transfer and a dma transfer cannot be su spended by an interrupt request, continuous dma activity will increase interrupt delay . a n nmi request halts any dma activity, however, enabling the cpu to respond promptly to the request. 4.24 pulse width demodulation note: there is no support for analog - to - digital conversion. this feature provides a means of measuring the width of a pulse in both its high and low phases. it s enabled by the pwd bit (bit [6]) in the syscon. tmrin0, tmrin1, int2, and int4 are internally configured to support the detection of rising and falling edges on the pwd pin ( int2/int0_n/pwd ) and to enable either timer0 or timer1 , depending on whethe r the signal is high or low (see figure 11). because they are not used in this mode, the tmrin0 , tmrin1 , and int4 pins are available as pio pins. figure 11 . typical waveform at the int2/int0_n/pwd pi n int2 int4 int2 interrupts generated timer1 enable d timer0 enabled ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 60 of 1 54 1 - 888 - 824 - 4184 the current count of timer1 for int2 and timer0 for int4 should be inspected by the isr to determine the pulse width. the timer count register should then be reset by the isr in readiness for the next pulse. the timer count rate (one - fourth of the proce ssor clock rate) determines the maximum resolution of the timers. to avoid the delay in servicing a timer interrupt in cases where the pulse width is short, the int2 and int4 request bits in the interrupt request register may be polled. i n cases where th e pulse width is greater than the maximum count of the timer, detection is achieved either by monitoring the maximum count (mc) bit of the respective timer or by enabling the timer interrupt requests by setting the int bit in the respective timer mode and control register. 4.25 asynchronous serial ports there are two independent asynchronous serial ports that employ standard industry communication protocols in their implementation of full duplex, bi - directional data transfers. functioning independently, either port may be the source or dest ination of dma transfers. the following features are supported: full - duplex data transfers 7 - , 8 - , or 9 - bit data transfers odd, even, or no parity one or two stop bits break characters of two lengths error detection provided by parity, framing, or overrun errors hardware handshaking achieved with the following selectable control signals: C clear to send ( cts_n ) C enable receiver request ( enrx_n ) C ready to send ( rts_n ) C ready to receive ( rtr_n ) dma to and from the ports each port h as its own maskable interrupts 9 - bit multidrop protocol ea ch port has an independent baud - rate generator maximum baud rate is 1/16 of the processor clock transmit and receive lines are double buffered 4.26 programmable i/o thirty - two pins are programmable as i /o signals (pio) . t able 15 presents them in both numeric and alphabetic order. because p rogramming a pin as a pio disables its normal function, it should be done only if the normal function is not required. a pio pin can be programmed as an ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 61 of 154 1 - 888 - 824 - 4184 input or out put with or without a weak pull - up or pull - down . a pio pin can be also programmed as an open - drain output. each pio pin regains default status after a por . table 15 . default status of pio pins at reset pio no. associated pin pow er - on reset status associated pin a power - on reset status 0 tmrin1 input with pullup a17 7 normal operation a 1 tmrout1 input with pulldown a18 8 normal operation a 2 pcs6_n/a2 input with pullup a19 9 normal operation a 3 pcs5_n/a1 normal operation a cts0_n/enrx0_n 21 input with pullup 4 dt/r_n normal operation a den_n/ds_n 5 normal operation a 5 den_n/ds_n normal operation a drq0/int5 12 input with pullup 6 srdy normal operation a drq1/int6 13 input with pullup 7 b a17 normal operation a dt/r_n 4 no rmal operation a 8 b a18 normal operation a int2/inta0_n/pwd 31 input with pullup 9 b a19 normal operation a int4 30 input with pullup 10 tmrout0 input with pulldown mcs0_n 14 input with pullup 11 tmrin0 input with pullup mcs1_n 16 input with pullup 12 drq0/int5 input with pullup mcs2_n 24 input with pullup 13 drq1/int6 input with pullup mcs3_n/rfsh_n 25 input with pullup 14 mcs0_n input with pullup pcs0_n 16 input with pullup 15 mcs1_n input with pullup pcs1_n 17 input with pullup 16 pcs0_n inp ut with pullup pcs2_n/cts1_n/enrx1_n 18 input with pullup 17 pcs1_n input with pullup pcs3_n/rts1_n/rtr1_n 19 input with pullup 18 pcs2_n/cts1_n/enrx1_n input with pullup pcs5_n/a1 3 input with pullup 19 pcs3_n/rts1_n/rtr1_n input with pullup pcs6_n /a2 2 input with pullup 20 rts0_n/rtr0_n input with pullup rts0_n/rtr0_n 20 input with pullup 21 cts0_n/enrx0_n input with pullup rxd0 23 input with pullup 22 txd0 input with pullup rxd1 28 input with pullup 23 rxd0 input with pullup s6/lock_n/clkd iv2 29 input with pullup 24 mcs2_n input with pullup srdy 6 normal operation d 25 mcs3_n/rfsh_n input with pullup timrin0 11 input with pullup 26 b,c uzi_n input with pullup tmrin1 0 input with pullup 27 txd1 input with pullup tmrout0 10 input with p ulldown 28 rxd1 input with pullup tmrout1 1 input with pulldown 29 b,c s6/lock_n/clkdiv2 input with pullup txd0 22 input with pullup 30 int4 input with pullup txd1 27 input with pullup 31 int2/inta0_n/pwd input with pullup uzi_n 26 input with pullup a input with pullup when used as pio. b emulato rs use these pins and also s2_n C s0_n, res_n, nmi, clkouta, bhe_n , ale, ad15 C ad0 , and a16 C a0. c if bhe_n/aden_n (ia186es) or rfsh_n/aden_n (ia188es) is held low during por , these pins will revert to normal opera tion. d input with pulldown option available when used as pio. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 62 of 154 1 - 888 - 824 - 4184 these default status setting s may be changed as desired. after por, a19 C a17 , the three most significant bits of the address bus , start with their normal function , allowing the processor to be gin fetching instructions from the boot address ffff0h. normal function is also the default setting for dt/r_n , den_n , and srdy after por . if the ad15 C ad0 bus override is enabled , s6/clkdiv2_n and uzi_n automatically return to normal operation. the ad15 C ad0 bus override is enabled if either the bhe_n/aden_n for the ia186es or the rfsh2_n/aden_n for the ia188es is held low during por . 5. peripheral architecture 5.1 control and registers the on - chip peripherals in the ia186es/ia188es are controlled from a 256 - by te block of internal registers. although these registers are actually located in the peripherals they control, they are addressed within a sin gle 256 - byte block of i/o space and are treated as a functional unit. a list of these registers is presented in table 16. although a named register may be 8 bits, write operations performed on the ia188es should be 8 - bit writes, result ing in 16 - bit data transfers to the peripheral control block (pcb) register. only word reads should be performed to the pcb registe rs . if unaligned read and write accesses are performed on either the ia186es or ia188es, indeterminate behavior may result . note: adhere to the se direction s while writing code to avoid errors . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 63 of 154 1 - 888 - 824 - 4184 table 16 . peripheral control regi sters register name offset register name offset peripheral control block registers timer registers pcb relocation register feh timer 2 mode and control register 66h reset configuration register f6h timer 2 max count compare a register 62h processor release level register f4h timer 2 count register 60h auxiliary configuration register f2h timer 1 mode and control register 5eh system configuration register f0h timer 1 max count compare b register 5ch watchdog timer control register e6h timer 1 max c ount compare a register 5ah enable rcu register e4h timer 1 count register 58h clock prescaler register e2h timer 0 mode and control register 56h memory partition register e0h timer 0 max count compare b register 54h dma registers timer 0 max count com pare a register 52h dma1 control register dah timer 0 count register 50h dma1 transfer count register d8h interrupt registers dma1 destination address high register d6h serial port 0 interrupt control register 44h dma1 destination address low registe r d4h serial port 1 interrupt control register 42h dma1 source address high register d2h int4 interrupt control register 40h dma1 source address low register d1h int3 interrupt control register 3eh dma0 control register cah int2 interrupt control re gister 3ch dma0 transfer count register c8h int1 interrupt control register 3ah dma0 destination address high register c6h int0 interrupt control register 38h dma0 destination address low register c4h dma1/int6 interrupt control register 36h dma0 so urce address high register c2h dma0/int5 interrupt control register 34h dma0 source address low register c0h timer interrupt control register 32h chip - select registers interrupt status register 30h pcs_n and mcs_n auxiliary register a8h interrupt re quest register 2eh mid - range memory chip - select register a6h interrupt in - service register 2ch peripheral chip - select register a4h interrupt priority mask register 2ah low - memory chip - select register a2h interrupt mask register 28h upper - memory chip - select register a0h interrupt poll status register 26h serial port 0 registers interrupt poll register 24h serial port 0 baud rate divisor register 88h end - of - interrupt (eoi) register 22h serial port 0 receive register 86h interrupt vector register 20h serial port 0 transmit register 84h serial port 1 registers serial port 0 status register 82h serial port 1 baud rate divisor register 18h serial port 0 control register 80h serial port 1 receive register 16h pio registers serial port 1 transm it register 14h pio data 1 register 7ah serial port 1 status register 12h pio direction register 78h serial port 1 control register 10h pio mode 1 register 76h pio data 0 register 74h pio direction 0 register 72h pio mode 0 register 70h ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 64 of 154 1 - 888 - 824 - 4184 5.1.1 relreg (0feh) the peripheral control block rel ocation reg ister maps the entire peripheral control block register bank to either i/o or memory space. in addition, relreg contains a bit that places the interrupt controller in either master or slave mode. the relreg contains 20ffh at reset (see table 17). table 17 . peripheral control block rel ocation reg ister 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res erved s/mn res erved io/mn ra [19 C 8] bi t [ 15 ] reserved. bit [ 14 ] s/mn when set to 1 , this bit places the interrupt controller into slave mode. when 0 , it is in master mode. bi t [13] reserved. b it [ 12 ] io/mn when set to 1 , the peripheral control block is mapped into memory space. when 0, this bit maps the peripheral co ntrol block register bank into io space. b its [ 11 C 0 ] ra [19 C 8] sets the base address (upper 12 bits) of the peripheral con trol block register bank. ra [7 C 0 ] default to zero. w hen b it [ 12 ] ( io/mn ) is set to 1 , ra [19 C 16] are ignored. 5.1.2 rescon (0f6h) the res et con figuration register latches user - defined information present at specified pins at the rising edge of reset. the contents of this register are read - only and remain valid until the next reset. the rescon contains user - defined information at reset (see table 18) . table 18 . reset configuration reg ister 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rc [15 C 0] b its [ 15 C 0 ] rc [15 C 0] at the rising edge of reset, the values of specified pins ( ad 15 C ad0 for the ia186es and ao 15 C ao 8 and ad 7 C ad 0 for the ia188es) are latched into this register. 5.1.3 prl (0f4h) the p rocessor r elease l evel register contains a code corresponding to the latest pr ocessor production release. the prl is a read - only register . the prl contains 1100h (see table 19) . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 65 of 154 1 - 888 - 824 - 4184 table 19 . p rocessor r elease l evel register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prl [7 C 0] res b its [ 15 C 8 ] prl [7 C 0] the la test processor release level. prl value processor release level 10h a 11h b 12h c 13h d 14h e bits [7 C 0] reserved. 5.1.4 auxcon (0f2h) the aux ili ary con figuration register configures the flow control signals for the asynchronous serial ports. auxcon cont rols data bus width (8 - or 16 - bit) for lower memory, middle memory, and io accesses and contains 0000h at reset (see table 20) . table 20 . aux iliary con figuration register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res enrx1 rts1 enrx 0 rts0 lsiz msiz iosiz b it [ 15 C 7 ] reserved. bit [ 6 ] enrx1 when set to 1, the cts1_n/enrx1_n pin functions as cts1_n . when 0, it functions as enrx1_n . bit [ 5 ] rts1 when set to 1, the rtr1_n/rts1_n pin functions as rts1_n . when 0, it functions as rtr 1_n. bit [ 4 ] enrx0 when set to 1, the cts0_n/enrx0_n pin functions as cts0_n . when 0, it functions as enrx0_n . bit [ 3 ] rts0 when set to 1, the rtr0_n/rts0_n pin functions as rts0_n . when 0, it functions as rtr0_n . bit [ 2 ] lsiz (ia186es only) when s et to 1, 8 - bit data access es are performed in lower chip - select ( lcs_n ) space. when 0, 16 - bit data access es are performed. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 66 of 154 1 - 888 - 824 - 4184 bit [ 1 ] msiz (ia186es only) when set to 1, 8 - bit data access es are performed in middle chip - select ( mcs_n ) space and peripheral ch ip - select space ( psc_n but only if pcs_n is mapped to memory). when 0, 16 - bit data access es are performed. bit [ 0 ] iosiz (ia186es only) when set to 1, 8 - bit data access es are performed in all i/o space. when 0, 16 - bit data access es are performed. 5.1.5 sysco n (0f0h) the system con figuration register controls several miscellaneous system i/o and timing functions. the syscon contains 0000h at reset (see table 21) . table 21 . system con figuration register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 psen mcsbit dsden pwd cbf cbd caf cad res f2 f1 f0 bit [15] psen when set to 1, enables the power - save mode causing the internal operating clock to be divided by the value in f2 C f0 . external or internal interrupts clear psen automatically . software interrupts and exception s do not . note: t he value of psen is not re stored upon execution of an iret instruction. bit [ 14 ] mcsbit when set to 1, mcs0_n is active over the entire mcs range, thus freeing msc2 _n and mcs1_n to be used as pio . when 0, it behaves normally. bit [ 13 ] dsden when set to 1, the ds_n/den_n pin f unctions as ds_n . when 0, it functions as den_n . see the individual pin descriptions for details of data strobe ( ds_n ) mode versus data enable ( den_n ) mode. bit [12] pwd when set to 1, the pulse width demodulator is enabled. when 0, it is disabled. bi t [ 11 ] cbf when set to 1, the clkoutb output follows the input crystal (pll) frequency. when 0, it follows the internal clock frequency after the clock divider. bit [ 10 ] cbd when set to 1, the clkoutb output is driven low. when 0, it is driven as an output per the cbf bit. bit [ 9 ] caf when set to 1, the clkouta output follows the input crystal (pll) frequency. when 0, it follows the internal clock frequency after the clock divider. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 67 of 154 1 - 888 - 824 - 4184 bit [ 8 ] cad when set to 1, the clkouta output is driven low. whe n 0, it is driven as an output per the cbf bit. bits [ 7 C 3 ] reserved the bits read back as zeros. bits [ 2 C 0 ] f2 C f0 these bits control th e clock divider as shown below. note : psen must be 1 for the clock divider to function. f2 f1 f0 divider factor 0 0 0 divide by 1 (2 0 ) 0 0 1 divide by 2 (2 1 ) 0 1 0 divide by 4 (2 2 ) 0 1 1 divide by 8 (2 3 ) 1 0 0 divide by 16 (2 4 ) 1 0 1 divide by 32 (2 5 ) 1 1 0 divide by 64 (2 6 ) 1 1 1 divide by 128 (2 7 ) 5.1.6 wdtcon (0e6h) the w atch d og t imer con trol register provides c ontr ol and status for the wdt . the wdtcon contains c080h at reset (see table 22) . table 22 . w atch d og t imer con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ena wrst rstflag nmiflag test res count bit [ 15 ] ena when set to 1, the wdt is enabled. when 0, it is disabled. bit [ 14 ] wrst when set to 1, an internal wdt reset is generated when the wdt timeout count ( count ) is reached. when 0, an nmi will be generated once wdt timeout count is reached and the nmifl ag bit is 0. if the nmiflag bit is 1, an internal wdt reset is generated when the wdt timeout count is reached. bit [ 13 ] rstflag when set to 1, a wdt timeout event has occurred. this bit may be cleared by software or by an external reset. bit [ 12 ] nmif lag when set to 1, a wdt nmi event has occurred. this bit may be cleared by software or by an external reset. if this bit is 1 when wdt timeout occurs, an internal wdt reset is generated regardless of the state of wrst . bit [ 11 ] test this bit is rese rved for chip test and should be always set to 0. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 68 of 154 1 - 888 - 824 - 4184 bits [ 10 C 8 ] reserved. bits [ 7 C 0 ] count control the timeout period for the wdt as follows: t timeout = 2 exponent / frequency ( equation 1 ) where: t timeout = the wdt timeout p eriod in seconds. frequency = the processor frequency in hertz. exponent = is based upon count as shown below: bit [ 7 ] bit [ 6 ] bit [ 5 ] bit [ 4 ] bit [ 3 ] bit [ 2 ] bit [ 1 ] bit [ 0 ] exponent 0 0 0 0 0 0 0 0 na x x x x x x x 1 10 x x x x x x 1 0 20 x x x x x 1 0 0 21 x x x x 1 0 0 0 22 x x x 1 0 0 0 0 23 x x 1 0 0 0 0 0 24 x 1 0 0 0 0 0 0 25 1 0 0 0 0 0 0 0 26 5.1.7 edram (0e4h) the e nable d ynamic ram refresh control register provides control and status for the refresh counter. the edram register conta ins 0000h at reset (see table 23) . table 23 . e nable d ynamic ram refresh control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en 0 0 0 0 0 0 t [8 C 0] bit [ 15 ] en when set to 1, the refresh counter is enabled and msc3_n is con figured to act as rfsh_n . clearing en clears the refresh counter and disables refresh requests. the refresh address is unaffected by clearing en . bits [ 14 C 9 ] reserved these bits read back as 0. bits [ 8 C 0 ] t [8 C 0] these bits hold the current value of the refresh counter. these bits are read - only. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 69 of 154 1 - 888 - 824 - 4184 5.1.8 cdram (0e2h) the c ount for dynamic ram (cdram) refresh control register determines the period between refresh cycles. the cdram register is undefined at reset (see table 24) . table 24 . c ount for dynamic ram refresh control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 rc [8 C 0] bits [ 15 C 9 ] reserved these bits read back as 0. bits [ 8 C 0 ] rc [8 C 0] these bits hold the clock count interval between refresh cycles. in power - save mode, the refresh counter value should be adjusted to account for the clock divider value in syscon. 5.1.9 mdram (0e0h) the m emory partition for d ynamic ram (mdram) refresh control register holds the a 19 C a 13 address bits of the 20 - bit base refresh address. the mdram register contains 0000h at reset (see table 25) . table 25 . m emory partition for d ynamic ram r efresh control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m [6 C 0] 0 0 0 0 0 0 0 0 0 bits [ 15 C 9 ] m [6 C 0] upper bits corresponding to address bits a19 C a13 of the 20 - bit memory refresh address. these bits are not available on the a19 C a0 bus. when using psram mode, m6 C m0 must be programmed to 0000000b. bits [ 8 C 0 ] reserved these bits read back as 0 . 5.1.10 d1con (0dah) and d0con (0cah) d ma con trol registers. dma control registers control operation of the two dma channels. the d0con and d1con registers are undefined at reset, except st which is set to 0 (see table 26) . table 26 . dma con trol registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dm/ion ddec dinc sm/i o n sdec sinc tc int syn1 C syn0 p tdrq ext chg st bn/w ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 70 of 154 1 - 888 - 824 - 4184 bit [ 15 ] dm/ion destination address space select selects memory or i/o space for the destination address. when dm/io is set to 1, the destination address is in memory space . w hen 0, it is in i/o space. bit [ 14 ] ddec destination decrement when set to 1 , automatically decrements the destination address after each transfer. the address is decremented by 1 or 2 , depending on the byte/word bit ( bn/w , b it [ 0 ] ). the address does not change if the increment and decrement bits are set to the same value (00b or 11b). bit [ 13 ] dinc destination increment when set to 1, automatically increments the destination address after each transfer. the address is incremented by 1 or 2 , depending on the byte/word bit ( bn/w , b it [ 0 ] ). the address does not change if the increment and decrement bits are set to the same value (00b or 11b). bit [ 12 ] sm/ion source address space select selects memory or i/o space for the source address. when set to 1, the sou rce address is in memory space. w hen 0, it is in i/o space. bit [ 11 ] sdec source decrem ent when set to 1, automatically decrements the destination address after each transfer. the address is decremented by 1 or 2, depending on the byte/word bit ( bn/w , b it [ 0 ] ). the address does not change if the increment and decrement bits are set to the same value (00b or 11b). bit [ 10 ] sinc source increment when set to 1, automatically increments the destination address after each transfer. the address is incremented by 1 or 2, depending on the byte/word bit ( bn/w , b it [ 0 ] ). the address does not change if the increment and decrement bits are set to the same value (00b or 11b). bit [ 9 ] tc terminal count . the dma decrements the transfer count for each dma transfer. when set to 1, the source or destination synchronized dma transfers terminate when the count reaches 0. w hen 0, they do not terminate when the count reaches 0. unsynchronized dma transfers always end when the count reaches 0, regardless of the setting of this bit. bit [ 8 ] int interrupt. when this bit is set to 1 , the dma channel generates an interrupt request on completion of the transfer count. however, for an interrupt to be generated, the tc bit must also be set to 1. bits [ 7 C 6 ] syn1 C syn0 synchronization type bits each select channel synchronization types as shown below . the value of these bits is ignored if tdrq ( bit [4]) is set to 1. a processor reset causes these bits to be set to 11b. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 71 of 154 1 - 888 - 824 - 4184 synchronization bit channel selection syn1 syn0 sync type 0 0 unsynchronized 0 1 source synchronized 1 0 destination synchronized 1 1 reserved bit [ 5 ] p relative priority . when set to 1 , selects high priority for this channel relative to the other channel during simultaneous transfers. bit [ 4 ] tdrq timer 2 synchronization. when set to 1, enables dma requests from timer 2. when 0 , disables them . bit [ 3 ] ext external interrupt enable bit . when set to 1, if the respective dma channel does not respond to changes on the drq pin , this pin functions as an int pin and the interrupt controller processes requests on the pin. when 0, it functions as a drq pin. bit [ 2 ] chg c hange start bit . this bit must be set to 1 to allow modification of the st bit during a write. during a write, when chg is set to 0, st is not changed when writing the control word. the result of reading this bit is always 0. bit [ 1 ] st start/stop dma channel. when set to 1, the dma channel is started. the chg bit must be set to 1 for this bit to be modified and only during the same register write. a processor reset causes this bit to be set to 0. bit [ 0 ] bn/w byte/word select. when set to 1, wor d transfers are selected. when 0, byte transfers are selected. note: word transfers are not supported if the chip selects are programmed for 8 - bit transfers. the ia188es does not support word transfers 5.1.11 d1tc (0d8h) and d0tc (0c8h) d ma t ransfer c oun t regi sters. the dma transfer count registers are maintained by each dma channel. they are decremented after each dma cycle. the state of the tc bit in the dma control register has no influence on this activity. but, if unsynchronized transfers are programme d or if the tc bit in the dma control word is set, dma activity ceases when the transfer count register reaches 0. the d0tc and d1tc registers are undefined at reset (see table 27) . table 27 . dma transfer count registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc15 C tc0 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 72 of 154 1 - 888 - 824 - 4184 bits [ 15 C 0] tc [15 C 0] dma transfer count contains the transfer count for the respective dma channel. its value is decremented after each transfer. 5.1.12 d1dsth (0d6h) and d0dsth (0c6h) the d ma d e st ination address h igh register. the 20 - bit destination address consists of these 4 b its combined with the 16 bits of the respective destination address low register. a dma transfer requires that two complete 16 - bit registers (high and low registers) be used for both the source and destination addresses of each dma channel involved. thes e four registers must be initialized. each address may be incremented or decremented independently of each other after each transfer. the addresses are incremented or decremented by two for word transfers and incremented or decremented by one for byte tr ansfers. they are undefined at reset (see table 28) . table 28 . d ma d e st ination address high register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dda19 C dda16 bits [ 15 C 4 ] reserved. bits [ 3 C 0 ] dda [19 C 16] dma destination add res s high bits are driven onto a 19 C a 16 during the write phase of a dma transfer. 5.1.13 didstl (0d4h) and d0dstl (0c4h) d ma d e st ination address l ow register. the 16 bits of these registers are combined with the 4 bits of the respective dma destination address h igh register to produce a 20 - bit destination address. the y are undefined at reset (see table 29) . table 29 . d ma d e st ination address l ow register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dda15 C dda0 bits [ 15 C 0] dda [15 C 0] dma destination addre ss low bits are driven onto a 19 C a 16 during the write phase of a dma transfer. 5.1.14 d1srch (0d2h) and d0srch (0c2h) d ma s ou rc e address h igh register. the 20 - bit source address consists of these 4 bits combined with the 16 bits of the res pective source address low register. a dma transfer requires that two complete 16 - bit registers in the pcb (high and low registers) be used for both the source and destination addresses of each dma channel involved. each channel requires that ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 73 of 154 1 - 888 - 824 - 4184 all four ad dress registers be initialized. each address may be independently incremented or decremented after each word transfer by 2 or by 1 for byte transfers. the y are undefined at reset (see table 30) . table 30 . d ma s ou rc e address h igh register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dsa1 9 C dsa16 bits [ 15 C 4 ] reserved . bits [ 3 C 0 ] dsa [19 C 16] dma source addres s high bits are driven onto a 19 C a 16 during the read phase of a dma transfer. 5.1.15 d1srcl (0d0h) and d0srcl (0c0h) d ma s ou rc e address l ow register. the 16 bits of these registers are combined with the 4 bits of the respective dma source address high register to produce a 20 - bit source address. the y are undefined at reset (see table 31) . table 31 . d ma s ou rc e address l ow register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsa15 C dsa0 bi ts [15 C 0] dsa [15 C 0] dma source address low bits are placed onto a15 C a0 during the read phase of a dma transfer. 5.1.16 mpcs (0a8h) mcs and pcs (mpcs) auxiliar y register. because this register controls more than one type of chip select, it is unlike other chip select control regi sters. the mpcs register contains information for mcs3_n C mcs0_n , pcs6_n C pcs5_n , and pcs3_n C pcs0_n . the mpcs register also contains a bit that configures the pcs6_n C pcs5_n pins as either chip selects or as alternate sources for the a2 and a 1 address bits. either a1 / a2 or pcs6_n C pcs5_n are selected to the exclusion of the other. when programmed for address bits, these outputs can be used to provide latched address bits for a2 and a1 . the pcs6_n C pcs5_n pins are high and n ot active on processor reset. when the pcs6_n C pcs5_n are configured as address pins , an access to the mpcs register causes them to activate . they do not require corresponding access to the pacs register to be activated. the value of the mpcs register is undefined at reset (see table 32) . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 74 of 154 1 - 888 - 824 - 4184 table 32 . mcs and pcs auxiliar y register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 m6 C m0 ex ms 1 1 1 r2 r1 C r0 bit [ 15 ] reserved set to 1. bits [ 14 C 8 ] m [6 C 0] mcs _n block size these seven bits determine the to tal memory block size for the mcs3 _n C mcs0 _n chip selects. the size is divided equally among the m . the relationship between m [6 C 0] and the size is shown below . select si zes of m6 C m0 by total block size total block size individual select size m6 C bit [ 7 ] ex pin selector this bit determines whe ther the pcs6_n C pcs5_n pins are configured as chip selects or as alternate outputs for a2 and a1 . when set to 1, they are configured as peripheral chip select pins . w hen 0, they become address bit s a1 and a2 , respectively. bit [ 6 ] ms memory/ i/o space selector determines whether the pcs_n pins are active during either memory or i/o bus cycles. when set to 1, the outputs are active for memory bus cycles . w hen 0 , they are active for i/o bus cycles. bits [ 5 C 3 ] reserved set to 1. bit [ 2 ] r2 ready mode this bit influences only the pcs6_n C pcs5_n chip selects. when set to 1, external ready is ignored. when 0, it is required. v alues determine the number of wait states to be inserted. bits [ 1 C 0 ] r [1 C 0] wait - state value these bits influence only the p cs6_n C pcs5_n chip selects. the ir value determines the number of wait states inserted into an access , depending on whether it i s to the pcs _n memory or i/o area. up to three wait states can be inserted ( r1 C r0 = 00b to 11b). ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 75 of 154 1 - 888 - 824 - 4184 5.1.17 mmcs (0a6h) m idrange m emory c hi p s elect (mmcs) register. four chip - select pins, mcs3_n C mcs0_n , are provided for use within a user - locatable memory block. excluding the areas associated with the ucs_n and lcs_n chip selects (and if mapped to memory, the address range of the peripheral chip selects, pcs6_n C pcs5_n and pcs3_n C pcs0_n ) , the memory block base address can be located anywhere within the 1 - mbyte memory address space. if the pcs_n chip selects are mapped to i/o space , the mcs_n address range can overlap the pcs_n address range. two registers program the midrange chip selects. the mmcs register determines the base address, the ready condition , and wait states of the memory block that are accessed through the mcs_n pins. the pcs_n and mcs_n auxiliary (mpcs) register configures th e block size. on reset , the mcs3_n C mcs0_n pins are not active. accessing with a write both the m mcs and mpcs registers activate these chip selects. unlike the ucs_n and lcs_n chip selects , the mcs3_n C mcs0_n outputs assert with the multiplexed ad address bus ( ad15 C ad0 or ao15 C ao8 and ad7 C ad0 ) , rather than the earlier timing of the a19 C a0 bus. if the a19 C a0 bus is used for address selection , the timing is delayed for a half cycle later than that for ucs_n and lcs_n . the value is undefined at reset (see ta ble 33) . table 33 . m idrange m emory c hip s elect register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ba19 C ba13 1 1 1 1 1 1 r2 r1 C r0 bits [ 15 C 9 ] ba [15 C 9] base address the value of the ba19 C ba13 determines the base address of the mem ory block that is addressed by the mcs_n chip select pins. these bits correspond to a19 C a13 of the 20 - bit memory address. the remaining bits a12 C a0 of the base address are always 0. C the base address may be any integer multiple of the size of the memory c lock selected in the mpcs register. for example, if the midrange block is 32 kbytes, the block could be located at 20000h or 28000h but not at 24000h. C if the lcs_n chip select is inactive, the base address of the midrange chip selects can be set to 00000h , because the lcs_n chip select is defined to be 00000h but is unused. because the base address must be an int eger multiple of the block size, a 512k mmcs block size can only be used with the lcs_n chip select inactive and the base address of the midrange chip selects set to 00000h. bits [ 8 C 3 ] reserved. set to 1. bit [ 2 ] r2 ready mode this bit determines the mcs_n chip selects ready mode. when set to 1, an external ready is ignored. when 0, an external ready is necessary. its value determines the number of wait states inserted into an access . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 76 of 154 1 - 888 - 824 - 4184 bits [ 1 C 0 ] r [1 C 0] wait - st ate value. the value of the se bits determines the number of wait states inserted in an access. up to three wait states can be inserted ( r1 C r0 = 00b to 11b). 5.1.18 pacs (0a4h) p eripher a l c hip s elec t register. the se peripheral chip selects are asserted over 256 - byte range with the same timing as the ad address bus. there are six chip selects, pcs6_n C pcs5_n and pcs3_n C pcs0_n that are use d in either the user - locatable memory or i/o blocks. excluding the areas use d by the ucs_n, lcs_n, and mcs_n chip selects, the memory block can b e located anywhere within the 1 - mbyte address space. these chip selects may also be configured to access the 64 - kbyte i/o space. programming the peripheral chip selects uses the peripheral chip select (pacs) and the pcs_n and mcs_n aux iliary (mpcs) register s . the pacs register establishes the base address, configures the ready mode, and determines the number of wait states for the pcs3_n C pcs0_n outputs. the mpcs register configures the pcs6_n C pcs5_n pins to be either chip selects or ad dress pins a1 and a2 . when these pins are configured as chip selects, the mpcs register determines the ready state and wait states for these output pins and whether they are active during memory or i/o bus cycles. these pins are activated as chip selects by writing to the two registers (pacs and mpcs). the y are not active on reset. to configure and activate them as address pins, it is necessary to write to both the pacs and mpcs registers. pins pcs6_n C pcs5_n can be configured for 0 to 3 wait states and pcs3_n C pcs0_n can be programmed for 0 to 15 wait states. the value of the pacs register is undefined at reset (see table 34) . table 34 . p eripher a l c hip s elec t register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ba19 C ba11 1 1 1 r3 r2 r1 C r0 bits [ 15 C 7 ] ba [19 C 11] base address bits correspond to bits [ 19 C 11 ] of the 20 - bit programmable base address of the peripheral chip select block and determine the base address . because i/o addresses are only 16 bits wide , if the pcs _n chip selects are mapped to i/o space, thes e bits must be set to 0000b. the pcs address ranges are shown below. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 77 of 154 1 - 888 - 824 - 4184 address ranges of pcs chip selects p cs _ n line range low high pcs0 _ n base address base address + 255 pcs1 _ n base address + 256 base address + 511 pcs2 _ n base address + 512 base addr ess + 767 pcs3 _ n base address + 768 base address + 1023 reserved n a n a pcs5 _ n base address + 1280 base address pcs6 _ n base address + 1536 base address bits [ 6 C 4 ] reserved. set to 1. bit [ 3 ] r [3] wait state value. s ee pcs3_n C pcs0_n wait - state encoding shown below . pcs3 _ n C pcs0 _ n wait - state encoding r3 r1 r0 wait states 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 5 1 0 1 7 1 1 0 9 1 1 1 15 bit [ 2 ] r [2] ready mode. when set to 1, external r eady is ignored. when 0, it is required. i n each case the number of wait states is determined according to the pcs3_n C pcs0_n wait - state encoding shown above . bits [ 1 C 0 ] r [1 C 0] wait - state value (s ee pcs3_n C pcs0_n wait - state encoding shown above) . the pcs6_n C pcs5_n and pcs3_n C pcs0_n pins are multiplexed with the pio pins. f or them to function as chip selects, the pio mode and direction settings for these pins must be set to 0 for normal operation. 5.1.19 lmcs (0a2h) the low - memory chip select (lmcs) register configures the low memory chip select provided to facilitate access to the interrupt vector table located at 00000h or the bottom of memory. the lcs_n pin is not active at reset. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 78 of 154 1 - 888 - 824 - 4184 the width of the data bus for the lcs_n space should be configured in the a uxcon register before activating the lcs_n chip select pin, by any write access to the lmcs register. the value of the lmcs register is undefined at reset except da, which is set to 0 (see table 3 5 ) . table 35 . low - memory chip sel ect register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ub2 C ub0 1 1 1 1 da pse 1 1 1 r2 r1 - r0 bit [ 15 ] reserved. set to 0 . bits [ 14 C 12 ] ub [2 C 0] upper boundary . these bits define the upper boundary of memory accessed by the lcs_n chip select. the lmcs block - size programming values shown below list the possible block - size configurations ( a 512 - kbyte max imum ). lmcs block - size programming values m emory block size ending address ub2 C ub0 64k 0ffffh 000b 128k 1ffffh 001b 256k 3ffffh 011b 512k 7ffffh 111b bits [ 11 C 8 ] reserved . set to 1. bit [ 7 ] da disable address when set to 1, the address bus is disabled, providing some measure of power savi ng. when 0, the address is driven onto the address bus ad15 C ad0 during the address phase of a bus cycle. this bit is set to 0 at reset. C if bhe_n/aden _n is held at 0 during the rising edge of res_n , the address bus is always driven, regardless of the sett ing of da. bit [ 6 ] pse psram mode enable when set to 1 , psram support for the lcs_n chip select memory space is enabled. the edram, mdram, and cdram rcu registers must be configured for auto refresh before psram support is enabled. setting the enable bit (en) in the enable rcu register (edram , offset e4h) configures the mcs3_n/rfsh_n as rfsh_n . bits [ 5 C 3 ] reserved. set to 1. b it [ 2 ] r2 ready mode when set to 1, the external ready is ignored. when 0, it is required. the value of the se bits determines the number of wait states inserted. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 79 of 154 1 - 888 - 824 - 4184 b its [ r1 C r0 ] r [1 C 0] wait - state value. the value of these bits determines the number of wait states inserted into an access to the lcs_n memory area. this number ranges from 0 to 3 (r1 C r0 = 00b to 11b) . 5.1.20 umcs (0a0h) the u pper m emor y c hip s elect register configures the umcs pin, used for the top of memory. on reset, the first fetch takes place at memory location ffff0h and thus this area of memory is usually used for instruction memory. the ucs_n defaults to an active state at reset with a memory range o f 64 kbytes (f0000h to fffffh), external ready required, and three wait states automatically inserted. the upper end of the memory range always ends at fffffh . t he lower end of this upper memory range is programmable. the value of the umcs register is f 03bh at reset (see table 36) . table 36 . u pper - m emor y c hip s elect register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 lb2 C lb0 0 0 0 0 da 0 1 1 1 r2 r1 C r0 bit [ 15 ] reserved. set to 1. bits [ 14 C 12 ] lb [2 C 0] lower boundary. these bits determine the bottom of the memory accessed by the ucs_n chip selects. the umcs block - size programming values shown below list the possible block - size configurations ( a 512 - kbyte max imum ) . umcs block - size programming values memory block size startin g address lb2 C C C C bits [ 11 C 8 ] reserved. set to 0 . bit [ 7 ] da disable address when set to 1, the address bus is disabled and the address is not driven on the address bus when ucs_n is asserted, providing some measure of power saving. when 0 , the address is driven onto the address bus ( ad15 C ad0 ) during the address phase of a bus cycle when ucs_n is asserted. this bit is set to 0 at reset. C if bhe_n/aden_n is held at 0 during the rising edge of res_n , the address bus is always driven, regardless of the setting of da. bit [ 6 ] reserved. set to 0. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 80 of 154 1 - 888 - 824 - 4184 bit [ 5 C 3 ] reserved. set to 1. bit [ 2 ] r2 ready mode when set to 1, the external ready is ignored. when 0, an external ready is required. the value of the se bits determines the number of wait states inserted. bits [ 1 C 0 ] r [1 C 0] wait - state value the value of these bits determines the number of wait st ates inserted into an access to the lcs_n memory area. this number ranges from 0 to 3 ( r1 C r0 = 00b to 11b). 5.1.21 sp0baud (088h) s erial p ort baud rate div isor registers. 5.1.22 sp1baud (018h) two baud - rate divisor regist ers, one for each port, allow the two ports to o perate at different baud rates. the value in these registers determines the number of internal processor cycles in one phase ( one half period) of the 16x serial clock. the contents of these registers must be adjusted to reflect the new processor clock fre quency if power - save mode is in effect. the baud rate divisor may be calculated from: b auddiv = (processor frequency/ (16 x baud rate)) (equation 2 ) by setting the bauddiv to 0001h, the maximum baud rate of 1/16 of the internal processor frequency clock is set. this provides a baud rate of 2500 kb ytes at 40 mhz. if the bauddiv is set to zero, transmission or reception of data does not occur. the ba ud rate tolerance is +3.0% and ? 2.5% with respect to the actual serial port baud rate, not the target baud rate (see table 37) . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 81 of 154 1 - 888 - 824 - 4184 table 37 . baud rates baud rate divisor based on cpu clock rate 20 mhz 25 mhz 33 mhz 40 mhz 300 4166 5208 6875 8333 600 2083 2604 3437 4166 1050 1190 1488 1964 2380 1200 1041 1302 1718 2083 1800 694 868 1145 1388 2400 520 651 859 1041 4800 260 325 429 520 7200 173 217 286 347 9600 130 162 214 260 19200 65 81 107 130 28800 43 54 71 86 38400 33 40 53 65 56000 22 28 36 45 5 7600 22 27 35 43 76800 16 20 26 32 115200 10 13 18 22 128000 9 12 16 19 153600 8 10 13 16 special 15 mhz 21 mhz 24 mhz 30 mhz 187500 5 7 8 10 the value of the sp0baud and sp1baud registers at reset is 0000h (see table 38) . table 38 . s erial p ort baud rate div isor register s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bauddiv bits [ 15 C 0 ] bauddiv baud rate divisor defines the divisor for the internal processor clock. 5.1.23 sp0rd (086h) and sp1rd (016h) s erial p ort r eceive registers. data received over the serial ports are stored in these registers until read. the data are received initially by the receive shift register (no software access) permitting data to be received while the previous data are being read. the status of these reg isters is indicated by the rdr bit (receive data ready) in the serial port status registers. setting the rdr bit to 1 indicates that there is valid data in the receive register. the rdr bit is cleared automatically when the receive register is read. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 82 of 154 1 - 888 - 824 - 4184 if h andshaking is employed, the control signals cts_n/enrx_n are deasserted while the receive register has valid unread data. the cts_n/enrx_n signal is reasserted after the data in the receive register is read. the value of the sp0rd and sp1rd registers is undefined at reset (see table 39) . table 39 . s erial p ort r eceive registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rdata bits [ 15 C 8 ] reserved . bits [ 7 C 0 ] rdata holds valid data while the rdr bit of the respective status register is set. 5.1.24 sp0td (084h) and sp1td (014h) s erial p ort t ransmit registers. dat a is written to these registers by software with the values to be transmitted by the serial port. double buffe ring of these transmitters allows for the transmission of data from the transmit shift registers (no software access), while the next data are written into the transmit registers. the temt and thre bits in the respective serial port status registers indi cate the status of these two pairs of registers. invoking handshaking requires that rts_n/rtr_n inputs be asserted before the transmitters can send any data which remain held in the transmit and shift registers without affecting the transmit pin. the valu e of the sptd registers is undefined at reset (see table 40) . table 40 . s erial p ort t ransmit registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tdata bits [ 15 C 8 ] reserved . bits [ 7 C 0 ] tdata holds the data to be transmitt ed. 5.1.25 sp0sts (082h) and sp1sts (012h) s erial p ort st atu s register. these registers store information concerning the current status of the respective ports. the value of the sp0sts and sp1sts registers is undefined at reset (see table 41). ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 83 of 154 1 - 888 - 824 - 4184 table 41 . s erial p ort st atu s register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved brk1 brk0 rb8 rdr thre fer oer per temt hs0 res bits [ 15 C 11 ] reserved . bit [ 10 ] brk1 long break detected a long break is a low signal level on the rxd pin for a period greater that 2 m + 3 bit times , where: m = start bit + number of data bits + parity bits + stop bit (equation 3 ) C should data reception be in progress when the bre ak starts, the reception of the current word will be completed and t he timing for the break will begin. because the stop bit will not be detected due to the break, this will generate a framing error . C detection of the break with the 2m + 3 bit time perio d can only be guaranteed if the break commences outside of a frame. note : this bit should be reset by software. bit [ 9 ] brk0 short break detected a short break is a low on the rxd pin for a period greater than m bit times (see equation 3 above ) . C should data reception be in progress when the break starts, the reception of the current word will be completed and the timing for the break will begin. because the stop bit will not be detected due to the break, this will generate a framing error. C detection of the break with the m bit time period can only be guaranteed if the break commences outside of a frame. note : this bit should be reset by softwar e. bit [8] rb8 received b it [ 8 ] this is the ninth d ata bit received in modes 2 and 3 ( see section 5.1.26, sp0ct (080h) and sp1ct (010h) ). note : this bit should be reset by software. bit [ 7 ] rdr receive data ready when this bit is 1 , it i ndicates that the respective sprd register conta ins valid data. this is a read - only bit and can be reset only by reading the corresponding receive register. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 84 of 154 1 - 888 - 824 - 4184 bit [ 6 ] thre transmit holding register empty when this bit is 1, it indicates that the correspon ding transmit holding register is ready to accep t data. this is a read - only bit. bit [ 5 ] fer framing error detected when the receiver samples the rxd line as low when a stop bit is expected (line high) , a framing error is generated setting this bit. not e : this bit should be reset by software. bit [ 4 ] oer overrun error detected when new data overwrites valid data in the receive register (because it has not been read) , an overrun error is detected setting this bit. note : this bit should be reset by sof tware. bit [ 3 ] per parity error detected when a parity error is detected in either mode 1 or 3, this bit is set. note : this bit should be reset by software. bit [ 2 ] temt transmitter empty when both the transmit shift register and the transmit register are empty, this bit is set indicating to software that it is safe to disable the transmitter. this bit is read - only. bit [ 1 ] hs0 handshake signal 0 this bit is the inverted value of cts_n and is read only. bit [ 0 ] res reserved . 5.1.26 sp0ct (080h) and sp1ct ( 010h) s erial p ort control registers. these registers control both transmit and receive parts of the respective serial ports. the value of the sp0ct and sp1ct registers is 0000h at reset (see table 42) . table 42 . s erial p ort con trol registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dma rsie brk tb8 fc txie rxie tmode rmode evn pe mode bits [ 15 C 13 ] dma dma control field these bits set up the respective ports for use with dma transfers as shown below . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 85 of 154 1 - 888 - 824 - 4184 dma control bits dma bits receive transmit 000b no dma no dma 001b dma0 dma1 010b dma1 dma0 011b reserved reserved 100b dma0 no dma 101b dma1 no dma 110b no dma dma 0 111b no dma dma1 C dma transfers to both serial ports are destination - synchronized operations. when the transmit holding register is empty, a new transfer is requested, corresponding with the assertion of the thre bit in the status register in non - dma mode. however, when configured for dma transfers, the respective transmit interrupt is disabled without regard for the txie bit. C dma transfers from both serial ports are source - synchronized operations. when the receive holding register contains valid dat a, a new transfer is requested, corresponding with the assertion of the rdr bit in the status register in non - dma mode. however, when configured for dma receives, the respective receive interrupt is disabled without regard for the rxie bit. this is despi te the fact that the rsie bit may still permit receive status interrupts, depending on its setting. C dma transfers do not preclude the use of hardware handshaking. C if either or both serial ports are configured for dma transfers, the dma request is internall y generated and the corresponding external dma signals, drq0 and/or drq1 do not play a role. bit [12] rsie receive status interrupt enable when an exception occurs during data reception, an interrupt request is generated if enabled by this bit ( rsie = 1) . interrupt requests are made for the error conditions listed ( brk0, brk1, oer, per, and fer ) in the serial port status register. bit [11] brk send break when this bit is set to 1, the txd pin is driven low overriding any data that may be in the course of being shifted out of the transmit shift register. note: see the definitions of long and short break in the serial port status register definition. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 86 of 154 1 - 888 - 824 - 4184 bit [ 10 ] tb8 transmit bit 8 this is the ninth data bit transmitted when in modes 2 and 3. this bit is cleared at each transmitted word and is not buffered. to transmit data with this bit set high, the following procedure is recommended. 1. the temt bit in the serial port status register must go high. 2. set the tb8 bit by writing it to the serial port control register. 3. write the transmit character to the serial port transmit register. bit [ 9 ] fc flow control enable this bit controls the hardware handshake (flow control) by enabling it when set to 1, and vice versa. the type of flow control depends on the value of the enrx0/enrx1 and rts0/rts1 bits in the auxcon register. C serial port 0 is a special c ase in that, if this bit is 1, the associated pins are used for flow control overriding the peripheral chip select signals. C this bit is 0 at reset. bit [ 8 ] txie transmitter ready interrupt enable this bit enables the gen eration of an interrupt request whenever the tr ansmit holding register is empty ( thre b it [ 1 ] ). the respective port does not generate interrupts when this bit is 0. interrupts continue to be generated as long as thre and the txie are 1. bit [ 7 ] rxie receive data ready interrupt enable this bit enab les the gen eration of an interrupt request whenever the receive register contains valid data ( rdr b it [ 1 ] ). the respective port does not generate interrupts when this bit is 0. interrupts continue to be generated as long as rdr and the rxie are 1. bit [ 6 ] tmode transmit mode the transmit section of the serial port is enabled when this bit is 1. conversely, the transmit section of the serial port is disabled when this bit is 0. bit [ 5 ] rmode receive mode the receive section of the serial port is enabled when this bit is 1. conversely, the receive section of the serial port is disabled when this bit is 0. bit [ 4 ] evn even parity when this bit is 1, even parity protocol is established. conversely, odd parity is established when this bit is 0. this bit is valid only when parity is enabled ( pe ). bit [ 3 ] pe parity enable parity is enabled when this bit is 1 and disabled when this bit is 0. bit [ 2 C 0 ] mode mode of operation these three bits establish the mode of operation of the respective serial port. the valid modes and their functions are shown below. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 87 of 154 1 - 888 - 824 - 4184 serial port mode settings mode description data bits parity bits stop bits 0 a data mode 0 7 C C C a data mode 5 7 or 8 1 or 0 2 6 a data mode 6 9 0 2 7 a data mode 7 8 or 9 1 or 0 2 a these were originally reserved modes that have been implemented to provide 2 stop bits. C mode 2 requires that the ninth data is set to a 1 state. otherwise, the character will be ignored b y the receiver. the transmit section, however, operates as if it were in mode 3. C this is designed to facilitate multi drop communication over a common serial data link. for this purpose, the port in question is initially programmed to mode 2 and for each dat a received with the ninth bit (b it [ 8 ] ) set as 1. it is compared by software with a unique identifier for this port. if the identifier comparison does not find a match, the port is left in mode 2. if the comparison finds an identifier match, the por t should be reprogrammed to mode 3 so that the ninth bit is allowed to be 0. C handshaking should only be employed in such a multidrop system by ports that are exchanging data (mode 3) to prevent multiple ports from attempting to drive the handshake signals. mode 2 does not support handshaking for this reason and should not be enabled. if it is possible that more than 2 ports be configured in mode 3 at the same time, handshaking should not be implemented. C mode 3 allows for 8 data bits if parity is enabled o r 9 data bits if parity is not enabled. if parity is not used, the ninth data bit for the transmit section is set by writing a 1 to the tb8 bit in the serial port control register. the ninth bit is read at the receive port from the rb8 bit in the serial port status register. C mode 4 allows for a start bit, 7 data bits, and a stop bit without parity, which is not available. 5.1.27 pdata1 (07ah) and pdata0 (074h) p io data registers. when a pio pin is configured as an output , the value in the corresponding pio data register bit is driven onto the pin. however, if the pio pin is configured ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 88 of 154 1 - 888 - 824 - 4184 as an input, the value on the pin is put into the corresponding bit of the pio data register. table 4 3 lists the default states for the pio pins. table 43 . pio pin assignments pio number associated pin name power - on reset status 0 tmrin1 input with pull - up 1 tmrout1 input with pull - down 2 pcs6/a2 input with pull - up 3 pcs5/a1 input with pull - up 4 dt/r_n normal operation a 5 den_n/ds_n normal operation a 6 srdy normal operation b 7 c a17 normal operation a 8 c a18 normal operation a 9 c a19 normal operation a 10 tmrout0 normal operation a 11 tmrin0 input with pull - up 12 drq0/int5 input with pull - up 13 drq1/int6 input with pull - up 14 mcs0_n input with pu ll - up 15 mcs1_n input with pull - up 16 pcs0_n input with pull - up 17 pcs1_n input with pull - up 18 pcs2_n/cts1_n/enrx1_n input with pull - up 19 pcs3_n/rts1_n/rtr1_n input with pull - up 20 rts0_n/rtr0_n input with pull - up 21 cts0_n/enrx0_n input with pull - up 22 txd0 input with pull - up 23 rxd0 input with pull - up 24 mcs2_n input with pull - up 25 mcs3_n/rfsh_n input with pull - up 26 c,d uzi input with pull - up 27 txd1 input with pull - up 28 rxd1 input with pull - up 29 c,d s6/lock_n/clkdiv2_n input with pull - up 30 int4 input with pull - up 31 int2/inta0_n/pwd input with pull - up a when used as a pio pin, it is an input with an available pull - up option. b when used as a pio pin, it is an input with an available pull - down option. c emulators use these pins. ( the s 2_n C s0_n, res_n, nmi, clkouta, bhe_n, ale, ad15 C ad0 , and a16 C a0 pins are used by emulators also.) d if bhe_n/aden_n is held low during por , these pins revert to normal operation. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 89 of 154 1 - 888 - 824 - 4184 the 32 pio pins initialize to either 00b or 01b as shown in t able s 4 4 and 45 . the value of the pdata registers is undefined at reset. table 44 . pdata 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdata (15 C 0) table 45 . pdata 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdata (31 C 16) bi ts [ 15 C 0 ] pdata [15 C 0] pio data 0 bits this register contains the values of the bits that are either driven on, or received fr om, the corresponding pio pins. d epending on its configuration each pin i s either an output or an input. the values of these b its correspond to those in the pio direction registers and pio mode registers. bits [ 15 C 0 ] pdata [31 C 16] pio data 1 bits this register contains the values of the bits that are either driven on, or received f rom, the corresponding pio pins. depending on its configuration each pin i s either an output or an input. the values of these bits correspond to those in the pio direction registers and pio mode registers the pio pins may be operated as open - drain outputs by: C maintaining the data constant in the app ropriate bit of the pio data register. C writing the value of the data bit into the respective bit position of the pio direction register, so that the output is either 0 or disabled depending on the value of the data bit. 5.1.28 pdir1 (078h) and pdir0 (072h) p io di r ection registers. each pio pin is configured as an input or an output by the corresponding bit in the pio direction register (see table 4 6 ) . table 46 . pio mode and pio direction settings pio mode pio direction pin function 0 0 normal operation 0 1 pio input with pullup/pulldown 1 0 pio output 1 1 pio input without pullup/pulldown ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 90 of 154 1 - 888 - 824 - 4184 the value of the pdir0 register is fc0fh at reset (see table 4 8 ). table 47 . pdir0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdir (15 C 0) the value of the pdir1 register is ffffh at reset (see table 4 8 ). table 48 . pdir1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdir (31 C 16) bits [ 15 C 0 ] pdir [15 C 0] pio direction 0 bits for each bit, if the value is 1 , th e pin is configured as an input. if 0 , as an output. the values of these bits correspond to those in the pio data registers and pio mode registers. bits [ 15 C 0 ] pdir [31 C 16] pio direction 1 bits for each bit, if the value is 1, th e pin is configured as an input. if 0 , as an output. the values of these bits correspond to those in the pio data registers and pio mode registers. 5.1.29 pmode1 (076h) and pmode0 (070h) p io mode registers. each pio pin is configured as an input or an output by the corresponding bit in the pio direction register. the bit number of pmod e corresponds to the pio number (s ee table 46, pio mode and pio direction settings ) . the value of the pmode0 register is 0000h at reset (see table 49 ). table 49 . pmode0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pmode (15 C 0) the value of the pmode1 register is 0000h at reset (see table 5 0 ). table 50 . pmode1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pmode (31 C 16) bits [ 15 C 0 ] pmode [15 C 0] pio mode 0 bits for each bit, if the value is 1, th e pin is configured as an input. if 0 , an output. the values of these bits correspond to those in the pio data registers and pio mode registers. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 91 of 154 1 - 888 - 824 - 4184 bits [ 15 C 0 ] pmode [31 C 16] pio mode 1 bits for eac h bit, if the value i s 1, the pin is configured as an input. if 0 , an output. the values of these bits correspond to those in the pio data registers and pio mode registers. 5.1.30 t1con (05eh) and t0con (056h) t ime r 0 and t ime r 1 mode and con trol registers. the s e registers control t he operation of timer0 and timer 1 , respectively. the value of the t0con and t1con registers is 0000h at reset (see table 5 1 ). table 51 . t ime r 0 and t ime r 1 mode and con trol registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en inhn i nt riu 0 0 0 0 0 0 mc rtg p ext alt cont bit [ 15 ] en enable bit the timer is enabled when the en bit is 1. the timer count is inhibited when the en bit is 0. setting this bit to 1 by writing to the t2con register requires that the inhn bit be set to 1 during the same write. this bit is write - only and can only be written if the inhn bit (bit [14]) is set to 1 in the same operation. bit [ 14 ] inhn inhibit bit gates the setting of the enable ( en ) bit. this bit must be set to 1 in the same write operat ion that sets the enable ( en ) bit. this bit always reads as 0. bit [ 13 ] int interrupt bit an interrupt request is generated when the count register reaches its maximum, mc = 1, by setting the int bit to 1. in dual maxcount mode, an interrupt request i s generated when the count register reaches the value in maxcount a or maxcount b. no interrupt requests are generated if this bit is set to 0. if an interrupt request is generated and then the enable bit is cleared before said interrupt is serviced, the interrupt request will remain. bit [ 12 ] riu register in use bit this bit is set to 1 when the maxcount register b is used to compare to the timer count value. it is set to 0 when the maxcount compare a register is used. bits [ 11 C 6 ] reserved. set to 0 . bit [ 5 ] mc maximum count when the timer reaches its maximum count , this bit is set to 1 regardless of the interrupt enable bit. this bit is also set every time maxcount com pare register a or b is reached when in dual maxcount mode. this bit may be used by software polling to monitor timer status rather than throu gh interrupts , if desired. bit [ 4 ] rtg retrigger bit . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 92 of 154 1 - 888 - 824 - 4184 bit [ 3 ] p prescaler bit p is ignored if external clocking is enabled ( ext = 1). timer 2 prescales the timer when p is set to 1. otherwise, the timer is incremented on every fourth clkout cycle. bit [ 2 ] ext external clock bit this bit determines whether an external or intern al clock is used. if ext = 1, an external clock is used. if ext = 0, an internal is used. bit [ 1 ] alt alternate compare bit if set to 1, the timer will count to maxcount compare register a, reset the count register to 0, and then count to maxcount comp are register b, reset the count register to 0 , and begin again at maxcount compare register a. if set to 0, the timer will count to maxcount compare register a, reset the count register to 0, and begin again at maxcount compare register a. maxcount compa re register b is not used in this case. bit [ 0 ] cont continuous mode bit the timer will run continuously when this bit is set to 1. the timer will stop after each count run and en will be cleared if the cont bit is set to 0. if cont = 1 and alt = 1, the respective timer counts to the maxcount compare a value and resets, the n it commences counting to maxcount compare b value, resets and ceases counting. 5.1.31 t2con (066h) t ime r 2 mode and con trol registers. this register cont rols the operation of the timer 2. the value of the t2con register is 0000h at reset (see table 5 2 ). table 52 . t ime r 2 mode and con trol registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en inhn int 0 0 0 0 0 0 0 mc 0 0 0 0 cont bit [ 15 ] en enable bit the timer is enabled when the en bit is 1. the timer count is inhibited when the en bit is 0. setting this bit to 1 by writing to the t2con register requires that the inh bit be set to 1 during the same write. this bit is write - only, but with the inhn bit set to 1 in the same write operation. bit [ 14 ] inh inhibit bit gates the setting of the enable ( en ) bit. this bit must be set to 1 in the same write operation that sets the enable ( en ) bit. this bit always reads as 0. bit [ 13 ] int interrupt bit an interrupt request is generated when the count register reaches its maximum, mc = 1, by setting the int bit to 1. bits [ 12 C 6 ] reserved. set to 0 . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 93 of 154 1 - 888 - 824 - 4184 bit [ 5 ] mc maximum count when the timer reaches its maximum count , this bit is set to 1 regardless of t he interrupt enable bit. this bit may be used by software polling to monitor timer status rather than through interrupts if desired. bits [ 4 C 1 ] reser ved. set to 0. bit [ 0 ] cont continuous mode bit the timer will run continuously when this bit is set to 1. the timer will stop after each count run and en will be cleared if this bit is set to 0. 5.1.32 t2compa (062h) , t1compb (05ch) , t1compa (05ah) , t0compb (054h) , and t0compa (052h) t ime r maxcount com pare registers. these registers contain the maximum count va lue that is compared to the re spective count register. timer0 and timer 1 have two of these compare registers each. if timer0 and/or timer 1 is/are configured to count and compare firstly to register a and then register b, the tmrout0 or tmrout1 signals m ay be used to generate various duty - cycle wave forms. timer 2 has only one compare register, t2compa. if one of these timer maxcount compare registers is set to 0000h, the respective timer will count from 0000h to ffffh before generating an interrupt reques t. for example , a timer configured in this manner with a 40 - mhz clo ck will interrupt every 6.5536 s. the value of these registers is 0000h at reset (see table 5 3 ). table 53 . t ime r maxcount com pare registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc15 C tc0 bits [ 15 C 0 ] tc [15 C 0] timer compare value the timer will count to the value in the respective register before resetting the count value to 0. 5.1.33 t2cnt (060h) , t1cnt (058h) , and t0cnt (050h) t imer c ou nt registers. these register s are incremented by one every four internal clock cycles if the relevant timer is enabled. the increment of timer0 and timer 1 may also be controlled by external signals tmrin0 and tmrin1 resp ectively, or prescaled by timer 2. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 94 of 154 1 - 888 - 824 - 4184 comparisons are made between the count registers and maxcount re gisters and action taken depende nt on achieving the maximum count. the value of these registers is 0000h at reset (see table 5 4 ). table 54 . t imer c ou nt registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc15 C tc0 bits [ 15 C 0 ] tc [15 C 0] timer count value this register has the value of the current count of the related timer that is incremented every fourth processor clock in internal clocked mode. alternatively , the register is incremented eac h ti me the timer 2 max count is reached if using timer2 as a prescaler. timer0 and timer 1 may be externally clocked by tmrin0 and tmrin1 signals. 5.1.34 sp0con (044h) and sp1con (042h) (master mode) s erial p ort interrupt con trol registers. these registers control the operation of the serial ports interrupt source. the value of these registers is 001fh at reset (see table 5 5 ). table 55 . s erial p ort interrupt con trol registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved res msk pr2 pr1 pr 0 bits [ 15 C 5 ] reserved. set to 0. bit [ 4 ] reserved. set to 1. bit [ 3 ] msk mask when 0, this bit enab les the serial port to cause an interrupt. when 1 , it prevents the serial port from generating an interrupt. bits [ 2 C 0 ] pr [2 C 0] priority. these bit s define the priority of the serial port interrupt in relation to other interrupt signals. the interrupt priority is the lowest at 7 upon reset. the values of pr2 C pr0 are shown below . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 95 of 154 1 - 888 - 824 - 4184 values of pr2 C pr0 by priority priority pr2 C 5.1.35 i4con (040h) (master mode) i nt 4 con trol register. the int4 signal is intended only for use in fully nested mode and is not available in cascade mode. the value of the i4con register is 000fh at rese t (see table 5 6 ). table 56 . i nt 4 con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ltm msk pr2 pr1 pr0 bits [ 15 C 5 ] reserved. set to 0. bit [ 4 ] ltm level - triggered mode the int4 interrupt may be edge - or level - t riggered, depending on the value of the bit. if ltm is 1, int4 is active high level - sensitive interrupt. if 0, it is a rising - edge triggered interrupt. the interrupt int4 must remain active (high) until serviced. bit [ 3 ] msk mask the int4 signal can c ause an interrupt if the msk bit is 0. the int4 signal cannot cause an interrupt if the msk bit is 1. bit [2 C 0 ] pr [2 C 0] priority these bits define the priority of the serial port interrupt in relation to other interrupt signals. the interrupt priority is the lowest at 7 upon reset. the values of pr2 C pr0 are shown above . 5.1.36 i3con (03eh) and i2con (03ch) (master mode) i nt 2 / i nt 3 con trol register. int2 and int3 are designated as interrupt type 0eh and 0fh , resp ectively. the int2 and int3 pins may be configured as the interrupt acknowledge pins inta0 and inta1, respectively, the signals in cascade mode. the value of these registers is 000fh at reset (see table 5 7 ). ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 96 of 154 1 - 888 - 824 - 4184 table 57 . i nt 2 / i nt 3 c on trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ltm msk pr2 pr1 pr0 bits [ 15 C 5 ] reserved. set to 0. bit [ 4 ] ltm level - triggered mode the int2 or int3 interrupt may be edge - or level - triggered depending on the value of this bit. if ltm is 1, int2 or int3 is an active high level - sensitive interrupt. if 0, it is a rising - edge triggered interrupt. the interrupt int2 or int3 must remain active (high) until acknowledged. bit [ 3 ] msk mask the int2 or int3 signal can cause an interrupt if the msk bit is 0. the int2 or int3 signal cannot cause an interrupt if the msk bit is 1. the interrupt mask register has a duplicate of this bit. bit [ 2 C 0 ] pr [2 C 0] priority these bits define the priority of the serial port interrupt int2 or int3 in re lation to other interrupt signals. the interrupt priority is the lowest at 7 upon reset. the values of pr2 C pr0 are shown above . 5.1.37 i1con (03ah) and i0con (038h) (master mode) i nt 0 / i nt 1 con trol register. iint0 and int1 are designated as interrupt type 0ch and 0dh , respectively. the int2 and int3 pins may be configured as the interrupt acknowledge pins inta0 and inta1 , respectively, the signals in cascade mode. the value of these registers is 000fh at reset (se e table 5 8 ). table 58 . i nt 0 / i nt 1 con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sfnm c ltm msk pr2 pr1 pr0 bits [ 15 C 7 ] reserved. set to 0. bit [ 6 ] spnm special fully nested mode this bit enables fully - nested mode for int0 or int1 when set to 1. bit [ 5 ] c cascade mode this bit enables cascade mo de for int0 or int1 when set to 1. bit [ 4 ] ltm level - triggered mode the int0 or int1 interrupt may be edge - or level - triggered depending on the value of the bit. if ltm is 1, int0 or int1 is an active high ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 97 of 154 1 - 888 - 824 - 4184 level - sensitive interrupt. if 0, it is a rising - edge triggered interrupt. the interrupt int0 or int1 must remain active (high) until acknowledged. bit [ 3 ] msk mask the int0 or int1 signal can cause an interru pt if the msk bit is 0. the int0 or int1 signal cannot cause an interrupt if the msk bit is 1. the interrupt mask register has a duplicate of this bit. bit [ 2 C 0 ] pr [2 C 0] priority these bits define the priority of the serial port interrupt int0 or int1 in relation to other interrupt signals. the interrupt priority is the lowest at 7 at reset. the values of pr2 C pr0 are shown above . 5.1.38 tcucon (032h) (master mode) t imer c ontrol u nit interrupt con trol register. the three timers, timer2, timer1, and timer0, have their interrupts assigned to types 08h, 12h, and 13h and are configured by this register. the value of these registers is 000fh at reset (see table 59 ). table 59 . t imer c ontrol u nit interrupt con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 pr1 pr0 bits [ 15 C 4 ] reserved. set to 0. bit [ 3 ] msk mask any of the interrupt sources may cause an interrupt if the msk bit is 0. the interrupt sources cannot ca use an interrupt if the msk bit is 1. the interrupt mask register has a duplicate of this bit. bit [ 2 C 0 ] pr [2 C 0] priority these bits define the priority of the serial port interrupts in relation to other interrupt signals. the interrupt priority is th e lowest at 7 upon reset. the values of pr2 C pr0 are shown above . 5.1.39 t2intcon (03ah) , t1intcon (038h) , and t0intcon (032h) (slave mode) t imer int errupt con trol register. the three timers, timer2, timer1, and ti mer0, each have an interrupt control register, whereas in master mode all three are masked and prioritized in one register (tcucon). the value of these registers is 000fh at reset (see table 6 0 ). table 60 . t imer int errupt con trol register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 C pr0 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 98 of 154 1 - 888 - 824 - 4184 bits [ 15 C 4 ] reserved. s et to 0. bit [ 3 ] msk mask any of the interrupt sources may cause an interrupt if the msk bit is 0. the interrupt sources cannot cause an interrupt if the msk bit is 1. the interrupt mask register has a duplicate of this bit. bit [ 2 C 0 ] pr [2 C 0] priority these bits define the priority of the serial port interrupts in relation to other interrupt signals. the interrupt priority is the lowest at 7 upon reset. the values of pr2 C pr0 are shown above . 5.1.40 dma1con/int6con (036h) and dma0con/int5con (034h) (master mode) dma and int errupt con trol register. the dma0 and dma1 interrupts have interrupt type 0ah and 0bh , respect ively. these pins are configured as external interrupts or dma requests in the respective dma control register. the value of these registers is 000fh at reset (see table 6 1 ). table 61 . dma and int errupt con trol register (master mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 C pr0 bits [ 15 C 4 ] reserved. set to 0. bit [ 3 ] msk mask any of the interrupt sources may cause an interrupt if the msk bit is 0. the interrupt sources cannot cause an interrupt if the msk bit is 1. the interrupt mask register has a duplicate of this bit. bits [ 2 C 0 ] pr [2 C 0] priority these bits define the priority of the serial port interrupts in relation to other interrupt signals. the interrupt priority is the lowest at 7 upon reset. the values of pr2 C pr0 are shown above . 5.1.41 dma1con/int6 (036h) and dma0con/int5 (034h) (slave mode) dma and int errupt con trol register . the two dma control registers maintain their original functions and addressing that they possessed in master mode. these pins are configured as external interrupts or dma requests in the respective dma control register. the value of these registers is 000fh at reset (see table 6 2 ). table 62 . dma and int er rupt con trol register (slave mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 C pr0 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 99 of 154 1 - 888 - 824 - 4184 bits [ 15 C 4 ] reserved. set to 0. bit [ 3 ] msk mask any of the interrupt sources may cause an interrupt if the msk bit is 0. the interrupt sources cannot caus e an interrupt if the msk bit is 1. the interrupt mask register has a duplicate of this bit. bits [ 2 C 0 ] pr [2 C 0] priority these bits define the priority of the serial port interrupts in relation to other interrupt signals. the interrupt priority is the lowest at 7 upon reset. the values of pr2 C pr0 are shown above . 5.1.42 intsts (030h) (master mode) int errupt st atu s register . the interrupt status register contains the interrupt request status of each of the three timers, timer2, timer1, and timer0 (see table 6 3 ). table 63 . int errupt st atu s register (master mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dhlt reserved tmr2 C tmr0 bit [ 15 ] dhlt dma halt dma activity is halted when this bit is 1. it is set to 1 automatically when any non - maskable interrupt occurs and is cleared to 0 when an iret instruction is executed. in terrupt handlers and other time - critical software may modify this bit directly t o disable dma transfers. however, the dhlt bit should not be modified by software if the timer interrupts are enabled as the function of this register as an interrupt request register for the timers would be compromised. bits [ 14 C 3 ] reserved. bit s [ 2 C 0 ] t mr [2 C 0] timer interrupt request when any of these bits is 1 , a pending interrupt request is in dicated by the respective timer. note: the tmr bit in the reqst register is a logical or of these timer interrupt requests. 5.1.43 intsts (030h) (slave mode) when nmi s occur , the interrupt status r egister controls dma operation and the interrupt request status of each of the three timers, timer2, timer1, and timer0 (see table 6 4 ). table 64 . int errupt st atu s register ( slave mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dhlt r eserved tmr2 C tmr0 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 100 of 154 1 - 888 - 824 - 4184 bit [ 15 ] dhlt dma halt dma activity is halted when this bit is 1. it is set to 1 automatically when any non - maskable interrupt occurs and is cleared to 0 when an iret instruction is executed. interrupt handlers and other time critical software may modify this bit directly t o disable dma transfers. however, the dhlt bit should not be modified by software if the timer interrupts are enabled as the function of this register as an interrupt request register for the timers would be compromised. bits [ 14 C 3 ] reserved. bit [ 2 C 0 ] tm r [2 C 0] timer interrupt request a pending interrupt request is indicated by the respective timer, when any of these bits is 1. note: the tmr bit in the reqst register is a logical or of these timer interrupt requests. 5.1.44 reqst (02eh) (master mode) interrupt req ue st register. this is a r ead - only register and such a read results in the status of the interrupt request bits presented to the interrupt controller. the reqst register is undefined on reset (see table 6 5 ). table 65 . interrupt req ue st register (master mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sp0 sp1 i4 i3 i2 i1 io d1/i6 d0/i5 res tmr bits [ 15 C 11 ] reserved. bit [ 10 ] sp0 serial port 0 interrupt request this is the serial port 0 interrupt state and when enabled is the logical or of all the se rial port 0 interrupt sources, thre, rdr, brk1, brk0, fer, per, and oer. bit [ 9 ] sp1 serial port 1 interrupt request this is the serial port 1 interrupt state an d when enabled is the logical or of all the se rial port 1 interrupt sources, thre, rdr, brk1, brk0, fer, per, and oer. bits [ 8 C 4 ] i [4 C 0] interrupt requests when any of these bits is set to 1 , it indicates that the relevant interrupt has a pending interr upt. bit [ 3 ] d1/i6 dma channel 1/interrupt 6 request when set to 1 , it indicates that either the dma channel 1 or int6 has a pending interrupt. bit [ 2 ] d0/i5 dma channel 0/interrupt 5 request when set to 1 , it indicates that either the dma channel 0 or int5 has a pending interrupt. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 101 of 154 1 - 888 - 824 - 4184 bit [ 1 ] reserved. bit [ 0 ] tmr timer interrupt request this is the timer interrupt state and is the logical or of the timer interrupt requests. when set to 1 , it indicates that the timer control unit has a pending interr upt. 5.1.45 reqst (02eh) (slave mode) this read - only register results in the status of interrupt request bits being presented to the interrupt controller. the status of these bits is available when this register is read. this register is read - only. when an int ernal interrupt request ( d1/i6, d0/i5, tmr2, tmr1 , or tmr0 ) occurs, the respective bit is set to 1. the internally generated interrupt acknowledge resets these bits. the reqst register contains 0000h on reset (see table 6 6 ). table 66 . interrupt req ue st register (slave mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tmr2 tmr1 d1/i6 d0/i5 res tmr0 bits [ 15 C 6 ] reserved. bit [ 5 ] tmr2 interrupt requests when set to 1, it indicates that timer 2 has a pending interrupt. bit [ 4 ] tmr1 interrupt requests when set to 1 , it indicates that timer 1 has a pending interrupt. bit [ 3 ] d1/i6 dma channel 1/interrupt 6 request when set to 1 , it indicates that either the dma channel 1 or int6 has a pending interrupt. bit [ 2 ] d0/i5 dma chan nel 0/interrupt 5 request when set to 1 , it indicates that either the dma channel 0 or int5 has a pending interrupt. bit [ 1 ] reserved. bit [ 0 ] tmr0 timer interrupt request when set to 1 , it indicates that timer 0 has a pending interrupt. 5.1.46 inserv (02ch ) (master mode) in - serv ice register. the interrupt controller sets the bits in this register when the interrupt is taken. the inserv register contains 0000h on reset (see table 6 7 ). ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 102 of 154 1 - 888 - 824 - 4184 table 67 . in - serv ice register (master mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sp0 sp1 i4 i3 i2 i1 io d1/i6 d0/i5 res tmr bits [ 15 C 11 ] reserved. bit [ 10 ] sp0 serial port 0 interrupt request this is the serial port 0 interrupt state. bit [ 9 ] sp1 serial port 1 interrupt request this is the serial port 1 interrupt state. bits [ 8 C 4 ] i [4 C 0] interrupt requests when any of these bits is set to 1 , it indicates that the relevant interrupt has a pending interrupt. bit [ 3 ] d1/i6 dma channel 1/interrupt 6 request when set to 1 , it indicates that either the dma channel 1 or int6 has a pending interrupt. bit [ 2 ] d0/i5 dma channel 0/interrupt 5 request when set to 1 it indicates that either the dma channel 0 or int5 has a pending interrupt. bit [ 1 ] reserved. bit [ 0 ] tmr timer interrupt request this is the timer interrupt state and is the logical or of the timer interrupt requests. when set to 1 , it indicates that the timer control unit has a pending interrupt. 5.1.47 inserv (02ch) (slave mode) this read - only register results in the status of interrupt request bits being presented to the interrupt controller. the status of these bits is available when this register is read. this re gister is read - o nly. when an internal interrupt request ( d1/i6, d0/i5, tmr2, tmr1 , and tmr0 ) occurs, the respective bit is set to 1. the internally generated interrupt acknowledge resets these bits. the reqst register contains 0000h on reset (see table 6 8 ). table 68 . in - serv ice register ( slave mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tmr2 tmr1 d1/i6 d0/i5 res tmr0 bits [ 15 C 6 ] reserved. bit [ 5 ] tmr2 timer2 interrupt in service timer 2 is being serviced when this bit is set to 1. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 103 of 154 1 - 888 - 824 - 4184 b it [ 4 ] tmr1 timer1 interrupt in service timer 1 is being serviced when this bit is set to 1. bit [ 3 ] d1/i6 dma channel interrupt 6 in service dma channel 1 or int6 is being serviced when this bit is set to 1. bit [ 2 ] d0/i5 dma channel interrupt 5 in se rvice dma channel 0 or int5 is being serviced when this bit is set to 1. bit [ 1 ] reserved. bit [ 0 ] tmr0 timer interrupt in service timer 0 is being serviced when this bit is set to 1. 5.1.48 primsk (02ah) (master and slave mode) pri ority m a sk register . this register contains a value that sets the minimum priority level that a maskable interrupt must have to generate an interrupt. the primsk register contains 0007h on reset (see table 69 ). table 69 . pri ority m a sk register 15 14 13 1 2 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prm2 C prm0 bits [ 15 C 3 ] reserved. set to 0. bits [ 2 C 0 ] prm [2 C 0] priority field mask this three - bit field sets the minimum priority necessary for a maskable interrupt to generate an int errupt. any maskable interrupt with a numerically higher value than that contained by these three bits, are masked. the values of pr2 C pr0 are shown above . C any unmasked interrupt may generate an interrupt if the priority level is set to 7. however, by way of example, if the priority level is set to 4, only unmasked interrupts with a priority of 0 to 5 are pe rmitted to generate interrupts. 5.1.49 imask (028h) (master mode) i nterrupt mask register. the interrupt mask register is read/write. setting a bit in this register is effectively the same as setting the msk bit in the corresponding interrupt control register. setting a bit to 1 masks the interrupt. the interrupt request is enabled when the corresponding bit is set to 0. the imask register contains 07fdh on reset (see table 7 0 ). ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 104 of 154 1 - 888 - 824 - 4184 table 70 . i nterrupt mask register (master mode) 15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sp0 sp1 i4 i3 i2 i1 io d1/i6 d0/i5 res tmr bits [ 15 C 11 ] reserved. bit [ 10 ] sp0 serial port 0 interrupt mask setting this bit to 1 is an indication that the serial port 0 interrupt is masked. bit [ 9 ] sp1 serial port 1 interrupt mask setting this bit to 1 is an indication that the serial port 0 interrupt is masked. bits [ 8 C 4 ] i [4 C 0] interrupt mask when any of these bits is set to 1 , it is an indication that the relevant interrupt is masked. bit [ 3 ] d1/i6 dma channel 1/interrupt 6 mask setting this bit to 1 , is an indication that either the dma channel 1 or int6 interrupt is masked. bit [ 2 ] d0/i5 dma cha nnel 0/interrupt 5 mask when set to 1 , it indicates that either the dma channel 0 or int5 interrupt is masked. bit [ 1 ] reserved. bit [ 0 ] tmr timer interrupt mask when set to 1 , it indicates that the timer control unit interrupt is masked. 5.1.50 imask (028h ) (slave mode) the interrupt mask register is read/write. setting a bit in this register has the effect of setting the msk bit in the corresponding interrupt control register. setting a bit to 1, masks the interrupt request. the interrupt request is ena bled when the corresponding bit is set to 0. the imask register contains 003dh on reset (see table 7 1 ). table 71 . i nterrupt mask register (slave mode) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tmr2 tmr1 d1/i6 d0/i5 res tmr0 bits [ 15 C 6 ] reserved. bit [ 5 ] tmr2 timer2 interrupt mask this bit provides the state of the mask bit in the timer interrupt control register. when set to 1, it indicates that the interrupt request is masked. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 105 of 154 1 - 888 - 824 - 4184 bit [ 4 ] tmr1 timer1 interrupt mask this bit provides the state of the mask bit in the timer interrupt control register. when set to 1, it indicates that the interrupt request is masked. bit [ 3] d1/i6 dma channel interrupt 6 mask this bit provides the state of the mask bit in the dma channel 0 or int5 interrupt control register. when set to 1, it indicates that the interrupt request is masked. bit [ 2 ] d0/i5 dma channel interrupt 5 mask this bit provides the state of the mask bit in the dma channel 1 or int6 interrupt control register. when set to 1, it indicates that the interrupt request is masked. bit [ 0 ] tmr0 timer interrupt mask this bit provides the state of the mask bit in the timer interrupt control register. when set to 1, it indicates that the interrupt request is masked. 5.1.51 pollst (026h) (master mode) poll st atus register. this register reflects the current state of the poll register and can be read without affecting its contents. however, the current interrupt is acknowledged and replaced by the next interrupt when the poll regis ter is read. the poll status register is read - only (see table 7 2 ). table 72 . poll st atus reg ister 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ireq reserved s4 C s0 bit [ 15 ] ireq interrupt request this bit is set to 1 when an interrupt is pending and during this state, the s4 C s0 bits contain valid data. bits [ 14 C 6 ] reserved. bit [ 5 C 0 ] s [5 C 0] poll status these bits show the interrupt type of the highest priority pending interrupt. 5.1.52 poll (024h) ( master mode) poll register. the current interrupt is acknowledged and replaced by the next interrupt when the poll register is read. the poll status register reflects the current state of the poll register and can be read without affecting its contents. the poll register is read - only (see table 7 3 ). ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 106 of 154 1 - 888 - 824 - 4184 table 73 . poll register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ireq reserved s4 C s0 bit [ 15 ] ireq interrupt request this bit is set to 1 when an interrupt is pending and during this state, the s4 C s0 bits contain valid data. bits [ 14 C 6 ] reserved. bit [ 4 C 0 ] s [4 C 0] poll status these bits show the interrupt type of the highest priority pending interrupt. 5.1.53 eoi (022h) e nd - o f - i nterrupt register (master mode) the in service flags of the inserv register are reset when a write is made to the eoi register. the interrupt service routine (isr) should write to the eoi to reset the is bit, in the inserv register, for the interru pt before executing an iret instruction than ends an interrupt service routine. because it is the most secure, the specific eoi reset is the preferred method for resetting the is bits. the eoi register is write - only (see table 7 4 ). table 74 . e nd - o f - i nterrupt register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nspec reserved s4 C s0 bit [ 15 ] nspeq non - specific eoi when set to 1 , this bit is a non - specific eoi. w hen 0 , it indicates the specific eoi. bits [ 14 C 5 ] reserved. bit [ 4 C 0 ] s [4 C 0] source interrupt type these bits show the interrupt type of the highest priority pending interrupt. 5.1.54 eoi (022h) specific e nd - o f - i nterrupt register (slave mode) specific e nd - o f - i nterrupt register. an in serv ice flag of a specific priority in the i nserv register is reset when a write is made to the eoi register. a three - bit, user - supplied priority - level value points to the in - service bit that is to be reset. writing this value to this register resets the specific bit. because it is the most secur e, the specific eoi reset is the preferred method for resetting the is bits. the eoi register is write - only and undefined at reset (see table 7 5 ). table 75 . specific e nd - o f - i nterrupt register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 l2 C l0 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 107 of 154 1 - 888 - 824 - 4184 bits [ 15 C 3 ] reserved. write as 0. bit [ 2 C 0 ] l [2 C 0] interrupt type the priority or the is (interrupt service) bit to be reset is encoded in these three bit s. writing to these bits causes the issuance of an eoi for th e interrupt type (see table 14, interrupt types ) . 5.1.55 intvec (020h) int errupt vec tor register (slave mode) the cpu shifts left 2 bits ( i.e., it multiplies by 4) an 8 - bit interrupt type, generated by the interrupt con troller, to produce an offset into the interrupt vector table. the intvec register is undefined at reset (see table 7 6 ). table 76 . int errupt vec tor register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 t4 C t0 0 0 0 bit s [15 C 8] reserved. read as 0. bits [7 C 3] t [4 C 0] interrupt type these five bits contain the five most significant bits of the types used for the internal interrupt. the least significant three bits of the interrupt type are supplied by the interrupt co ntroller, as set by the priority level of the interrupt request. bits [2 C 0] reserved. read as 0. 5.2 reference documents additional information on the operation and programming of the ia186es/ ia188es can be found in the following amd publications: am186 es a nd am188 es users manual (publication 21096) . am186 es/eslv and am188 es/eslv preliminary data sheet (publication 20002) . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 108 of 154 1 - 888 - 824 - 4184 6. ac specifications table 7 7 and table 7 8 present the alphabetic and numeric key s to waveform parameters , respectively . figure 12 presents the read cycle. figure 13 presents the multiple read cycles. table 79 presents the read cycle timing. figure 14 pre sents the write cycle. table 80 presents the wri te cycle timing. figure 15 presents the multiple write cycles. figure 16 presents the psram r ead cycle. table 8 1 presents the psram read cycle timing. figure 17 presents the psram write cycle. table 8 2 presents the psram write cycle timing. figure 18 presents th e psram refresh cycle. table 8 3 presents the psram refresh cycle timing. figure 19 presents the interrupt acknow ledge cycle. table 8 4 presents the interrupt acknowledge cycle timing. figure 20 presents th e software halt cycle. table 8 5 presents the soft ware halt cycle timing. figure 21 presents the active mode. figure 22 presents the power - save mode. table 8 6 presents the clock timing. figure 23 presents the srdy synchronous ready. figure 24 presents the ardy asynchronous r eady. figure 25 pre sents the peripherals. table 8 7 presents the ready and per ipheral timing. figure 26 and figure 27 present reset 1 and reset 2, respectively. figure 28 and figure 29 present the bus hold entering and bus hold leaving, respectively. table 8 8 presents the reset and bus hold timing. table 77 . alphabetic key to waveform parameters no. name description min a max a 49 tarych ardy resolution transition setup time 9 C 51 tarychl ardy inactive holding time 6 C 52 tarylcl ardy setup time 9 C 87 tavbl a address valid to whb_n/wlb_n low tchcl - 1.5 tchcl 14 tavch ad address valid to clock high 0 C 12 tavll ad address valid to ale low tchcl C 66 tavrl a address valid to r d_n low tclcl+tchcl C 65 tavwl a address valid to wr_n low tclcl+tchcl C 24 tazrl ad address float to rd_n active 0 C 45 tch1ch2 clkouta rise time 0 3 68 tchav clkouta high to a address valid 0 8 38 tchck x1 high time 7.5 C 44 tchcl clkouta high time tclcl/2 C 67 tchcsv clkouta high to lcs_n/usc_n valid 0 9 18 tchcsx mcs_n/pcs_n inactive delay 0 12 22 tchctv control active delay 2 0 10 64 tchcv command lines valid delay (after float) 0 12 63 tchcz command lines float delay 0 12 a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 109 of 154 1 - 888 - 824 - 4184 table 77. alphabetic key to waveform parameters (continued) no. name description min a max a 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 8 11 tchll ale inactive delay 0 8 79 tchrfd clkouta high to rfsh_n valid 0 12 3 tchsv status active d elay 0 6 69 tcicoa x1 to clkouta skew C 25 70 tcicob x1 to clkoutb skew C 35 39 tckhl x1 fall time C 5 36 tckin x1 period 25 66 40 tcklh x1 rise time C 5 46 tcl2cl1 clkouta fall time C 3 50 tclarx ardy active hold time 4 C 5 tclav ad address valid delay 0 12 6 tclax address hold 0 12 15 tclaz ad address float delay 0 12 43 tclch clkouta low time tclcl/2 C 37 tclck x1 low time 7.5 C 42 tclcl clkouta period 25 C 80 tclclx lcs_n inactive delay 0 9 81 tclcsl lcs_n active delay 0 9 16 tclcsv mcs_ n/pcs_n inactive delay 0 12 30 tcldox data hold time 0 C 7 tcldv data valid delay 0 12 2 tcldx data in hold 0 C 62 tclhav hlda valid delay 0 7 82 tclrf clkouta high to rfsh_n invalid 0 12 27 tclrh rd_n inactive delay 0 10 25 tclrl rd_n active delay 0 10 4 tclsh status inactive delay 0 6 48 tclsry srdy transition hold time 3 C 55 tcltmv timer output delay 0 12 83 tcoaob clkouta to clkoutb skew 3 1 20 tcvctv control active delay 1 C 10 31 tcvctx control inactive delay 0 10 21 tcvdex den_n inacti ve delay 0 9 17 tcxcsx mcs_n/pcs_n hold from command inactive tclch C 98 tdshdiw ds_n high to data invalid (write) 0 tchcl 41 tdshlh ds_n inactive to ale inactive tclch C a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 110 of 154 1 - 888 - 824 - 4184 table 77. alphabetic key to waveform parameters (continued) n o. name description min a max a 1 tdvcl data in setup 10 C 19 tdxdl den_n inactive to dt/ r_n low 0 C 58 thvcl hld setup time 10 C 53 tinvch peripheral setup time 10 C 54 tinvcl drq setup time 10 C 86 tlcrf lcs_n inactive to rfsh_n active delay 2tclcl C 23 tlhav ale high to address valid 7.5 C 10 tlhll ale width tclch - 5 C 13 tllax ad address hold from ale inactive tchcl C 61 tlock maximum pll lock time C 0.5 84 tlrll lcs_n precharge pulse width tclcl+tclchh C 57 tresin res_n setup time 10 C 85 trf cy rfsh_n cycle time 6tclcl C 29 trhav rd_n inactive to ad address active tclcl C 59 trhdx rd_n high to data hold on ad bus 0 C 28 trhlh rd_n inactive to ale high tclch C 26 trlrh rd_n pulse width tclcl C 47 tsrycl srdy transition setup time 10 C 35 twhdex wr_n inactive to den_n inactive tclch C 34 twhdx data hold after wr_n tclcl C 33 twhlh wr_n inactive to ale high tclch C 32 twlwh wr_n pulse width 2tclcl C a in nanoseconds. table 78 . numeric key to waveform parameters no. name description min a max a 1 tdvcl data in setup 10 C 2 tcldx data in hold 0 C 3 tchsv status active delay 0 6 4 tclsh status inactive delay 0 6 5 tclav ad address valid delay 0 12 6 tclax address hold 0 12 7 tcldv data valid delay 0 12 8 tchd x status hold time 0 C 9 tchlh ale active delay 0 8 10 tlhll ale width tclch - 5 C 11 tchll ale inactive delay 0 8 12 tavll ad address valid to ale low tclch C 13 tllax ad address hold from ale inactive tchcl C a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 111 of 154 1 - 888 - 824 - 4184 table 78 . numeric key to waveform parameters (continued) no. name description min a max a 14 tavch ad address valid to clock high 0 C 15 tclaz ad address float delay 0 12 16 tclcsv mcs_n/pcs_n inactive delay 0 12 17 tcxcsx mcs_n/pcs_n hold from command inactive tclch C 18 t chcsx mcs_n/pcs_n inactive delay 0 12 19 tdxdl den_n inactive to dt/ r_n low 0 C 20 tcvctv control active delay 1 0 10 21 tcvdex den_n inactive delay 0 9 22 tchctv control active delay 2 0 10 23 tlhav ale high to address valid 7.5 C 24 tazrl ad addres s float to rd_n active 0 C 25 tclrl rd_n active delay 0 10 26 trlrh rd_n pulse width tclcl C 27 tclrh rd_n inactive delay 0 10 28 trhlh rd_n inactive to ale high tclch C 29 trhav rd_n inactive to ad address active tclcl C 30 tcldox data hold time 0 C 31 tcvctx control inactive delay 0 10 32 twlwh wr_n pulse width 2tclcl C 33 twhlh wr_n inactive to ale high tclch C 34 twhdx data hold after wr_n tclcl C 35 twhdex wr_n inactive to den_n inactive tclch C 36 tckin x1 period 25 66 37 tclck x1 low tim e 7.5 C 38 tchck x1 high time 7.5 C 39 tckhl x1 fall time C 5 40 tcklh x1 rise time C 5 41 tdshlh ds_n inactive to ale inactive tclch C 42 tclcl clkouta period 25 C 43 tclch clkouta low time tclcl/2 C 44 tchcl clkouta high time tclcl/2 C 45 tch1ch2 clkouta rise time C 3 46 tcl2cl1 clkouta fall time C 3 47 tsrycl srdy transition setup time 10 C 48 tclsry srdy transi tion hold time 3 C 49 tarych ardy resolution transition setup time 9 C 50 tclarx ardy active hold time 4 C 51 tarychl ardy inactive holding time 6 C a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 112 of 154 1 - 888 - 824 - 4184 table 78 . numeric key to waveform parameters (continued) no. name description min a max a 52 tarylcl ardy setup time 9 C 53 tinvch peripheral setup time 10 C 54 tinvcl drq setup time 10 C 55 tcltmv timer output dela y 0 12 57 tresin res_n setup time 10 C 58 thvcl hld setup time 10 C 59 trhdx rd_n high to data hold on ad bus 0 C 61 tlock maximum pll lock time C 0.5 62 tclhav hlda valid delay 0 7 63 tchcz command lines float delay 0 12 64 tchcv command lines vali d delay (after float) 0 12 65 tavwl a address valid to wr_n low tclcl+tchcl C 66 tavrl a address valid to rd_n low tclcl+tchcl C 67 tchcsv clkouta high to lcs_n/usc_n valid 0 9 68 tchav clkouta high to a address valid 0 8 69 tcicoa x1 to clkouta skew C 25 70 tcicob x1 to clkoutb skew C 35 79 tchrfd clkouta high to rfsh_n valid 0 12 80 tclclx lcs_n inactive delay 0 9 81 tclcsl lcs_n active delay 0 9 82 tclrf clkouta high to rfsh_n invalid 0 12 83 tcoaob clkouta to clkoutb skew 3 11 84 tlrll lcs_n precharge pulse width tclcl+tclch C 85 trfcy rfsh_n cycle time 6tclcl C 86 tlcrf lcs_n inactive to rfsh_n active delay 2tclcl C 87 tavbl a address valid to whb_n/wlb_n low tchcl - 1.5 tchcl 98 tdshdiw ds_n high to data invalid (write) 0 tclcl 99 tplal pcs low to ale low C tclch a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 113 of 154 1 - 888 - 824 - 4184 figure 12 . read cycle ? c l k o u t a a 1 9 C a 0 s 6 / l o c k _ n a d 1 5 C a d 0 ( i a 1 8 6 e s ) , a d 7 C a d 0 ( i a 1 8 8 e s ) a o 1 5 C a o 8 ( i a 1 8 8 e s ) a l e r d _ n b h e _ n ( i a 1 8 6 e s ) l c s _ n , u c s _ n m c s _ n , p c s _ n d e n _ n / d s _ n d t / r _ n s 2 _ n C s 0 _ n u z i _ n ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 114 of 154 1 - 888 - 824 - 4184 figure 13 . multiple read cycles ? c l k o u t a a 1 9 C a 0 a d 1 5 C a d 0 ( i a 1 8 6 e s ) , a o 1 5 C a o 8 ( i a 1 8 8 e s ) l c s _ n , u c s _ n m c s _ n , p c s _ n s 2 _ n C s 0 _ n a l e r d _ n ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 115 of 154 1 - 888 - 824 - 4184 table 79 . read cycle timing no. name description min a max a general tim ing requirements 1 tdvcl data in setup 10 C 2 tcldx data in hold 0 C general timing responses 3 tchsv status active delay 0 6 4 tclsh status inactive delay 0 6 5 tclav ad address valid delay 0 12 6 tclax address hold 0 12 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 8 10 tlhll ale width tclch - 5 C 11 tchll ale inactive delay 0 8 12 tavll ad address valid to ale low tclch C 13 tllax ad address hold from ale inactive tchcl C 14 tavch ad address valid to clock high 0 C 15 tclaz ad addr ess float delay 0 12 16 tclcsv mcs_n/pcs_n inactive delay 0 12 17 tcxcsx mcs_n/pcs_n hold from command inactive tclch C 18 tchcsx mcs_n/pcs_n inactive delay 0 12 19 tdxdl den_n inactive to dt/ r_n low 0 C 20 tcvctv control active delay 1 0 10 21 tcvde x den_n inactive delay 0 9 22 tchctv control active delay 2 0 10 23 tlhav ale high to address valid 7.5 C 99 tplal pcs low to ale low C tclch read cycle timing responses 24 tazrl ad address float to rd_n active 0 C 25 tclrl rd_n active delay 0 10 26 trlrh rd_n pulse width tclcl C 27 tclrh rd_n inactive delay 0 10 28 trhlh rd_n inactive to ale high tclch C 29 trhav rd_n inactive to ad address active tclcl C 41 tdshlh ds_n inactive to ale inactive tclch C 59 trhdx rd_n high to data hold on ad bus 0 C 66 tavrl a address valid to rd_n low tclcl+tchcl C 67 tchcsv clkouta high to lcs_n/usc_n valid 0 9 68 tchav clkouta high to a address valid 0 8 a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 116 of 154 1 - 888 - 824 - 4184 figure 14 . write cycle ? c l k o u t a a 1 9 C a 0 s 6 / l o c k _ n a d 1 5 C a d 0 ( i a 1 8 6 e s ) , a d 7 C a d 0 ( i a 1 8 8 e s ) a o 1 5 C a o 8 ( i a 1 8 8 e s ) a l e w r _ n w h b _ n , w l b _ n ( i a 1 8 6 e s ) , w b _ n ( i a 1 8 8 e s ) b h e _ n ( i a 1 8 6 e s ) l c s _ n , u c s _ n m c s _ n , p c s _ n d e n _ n / d s _ n d t / r _ n s 2 _ n C s 0 _ n u z i _ n ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 117 of 154 1 - 888 - 824 - 4184 figure 15 . multiple write cycles ? c l k o u t a a 1 9 C a 0 a d 1 5 C a d 0 ( i a 1 8 6 e s ) , a o 1 5 C a o 8 ( i a 1 8 8 e s ) l c s _ n , u c s _ n m c s _ n , p c s _ n s 2 _ n C s 0 _ n a l e r d _ n ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 118 of 154 1 - 888 - 824 - 4184 table 80 . write cycle timing no. name description min a max a general timing requirements 1 tdvcl data in setup 10 C 2 tcldx data in hold 0 C general timing responses 3 tchsv status active delay 0 6 4 tclsh status inactive delay 0 6 5 tclav ad address valid delay 0 12 6 tclax address hold 0 12 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 8 10 tlhll ale width tclch - 5 C 11 tchll ale inactive delay 0 8 12 tavll ad address valid to al e low tclch C 13 tllax ad address hold from ale inactive tchcl C 14 tavch ad address valid to clock high 0 C 15 tclaz ad address float delay 0 12 16 tclcsv mcs_n/pcs_n inactive delay 0 12 17 tcxcsx mcs_n/pcs_n hold from command inactive tclch C 18 tc hcsx mcs_n/pcs_n inactive delay 0 12 19 tdxdl den_n inactive to dt/ r_n low 0 C 20 tcvctv control active delay 1 0 10 21 tcvdex den_n inactive delay 0 9 22 tchctv control active delay 2 0 10 23 tlhav ale high to address valid 7.5 C 99 tplal pcs low to ale low C tclch write cycle timing responses 30 tcldox data hold time 0 C 31 tcvctx control inactive delay 0 10 32 twlwh wr_n pulse width 2tclcl C 33 twhlh wr_n inactive to ale high tclch C 34 twhdx data hold after wr_n tclcl C 35 twhdex wr_n inact ive to den_n inactive tclch C 41 tdshlh ds_n inactive to ale inactive tclch C 65 tavwl a address valid to wr_n low tclcl+tchcl C 67 tchcsv clkouta high to lcs_n/usc_n valid 0 9 68 tchav clkouta high to a address valid 0 8 87 tavbl a address valid to w hb_n/wlb_n low tchcl - 1.5 tchcl 98 tdshdiw ds_n high to data invalid (write) 0 tclcl a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 119 of 154 1 - 888 - 824 - 4184 figure 16 . psram read cycle ? c l k o u t a a 1 9 C a 0 s 6 / l o c k _ n a d 1 5 C a d 0 ( i a 1 8 6 e s ) , a d 7 C a d 0 ( i a 1 8 8 e s ) a o 1 5 C a o 8 ( i a 1 8 8 e s ) a l e r d _ n l c s _ n 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns c l k o u t a a 1 9 - a 0 s 6 / l o c k _ n a d 1 5 - a d 0 / a d 7 - a d 0 a o 1 5 - a o 8 a l e r d _ n l c s _ n address address s6 lock_n s6 s6 address data address address address 66 68 8 7 1 2 9 23 11 10 59 24 26 28 25 27 5 81 80 84 ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 120 of 154 1 - 888 - 824 - 4184 table 81 . psram read cycle timing no. name description min a max a ge neral timing requirements 1 tdvcl data in setup 10 C 2 tcldx data in hold 0 C general timing responses 5 tclav ad address valid delay 0 12 6 tclax address hold 0 12 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 8 10 tlhll ale width tclch - 5 C 11 tchll ale inactive delay 0 8 12 tavll ad address valid to ale low tclch C 13 tllax ad address hold from ale inactive tchcl C 14 tavch ad address valid to clock high 0 C 15 tclaz ad address float delay 0 12 16 tclcsv mcs_n/pcs_n inactive delay 0 12 17 tcxcsx mcs_n/pcs_n hold from command inactive tclch C 18 tchcsx mcs_n/pcs_n inactive delay 0 12 19 tdxdl den_n inactive to dt/ r_n low 0 C 20 tcvctv control active delay 1 0 10 21 tcvdex den_n inactive delay 0 9 22 tchctv control active delay 2 0 10 23 tlhav ale high to address valid 7.5 C 99 tplal pcs low to ale low C tclch read cycle timing responses 30 tcldox data hold time 0 C 31 tcvctx control inactive delay 0 10 32 twlwh wr_n pulse width 2tclcl C 33 twhlh wr_n inactive to ale high tclch C 34 twhdx data hold after wr_n tclcl C 35 twhdex wr_n inactive to den_n inactive tclch C 41 tdshlh ds_n inactive to ale inactive tclch C 65 tavwl a address valid to wr_n low tclcl +tchcl C 67 tchcsv clkouta high to lcs_n/usc_n valid 0 9 68 tch av clkouta high to a address valid 0 8 87 tavbl a address valid to whb_n/wlb_n low tchcl - 1.5 tchcl 98 tdshdiw ds_n high to data invalid (write) 0 tclcl a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 121 of 154 1 - 888 - 824 - 4184 figure 17 . psram write cycle ? c l k o u t a a 1 9 C a 0 s 6 / l o c k _ n a d 1 5 C a d 0 ( i a 1 8 6 e s ) , a d 7 C a d 0 ( i a 1 8 8 e s ) a o 1 5 C a o 8 ( i a 1 8 8 e s ) a l e w r _ n l c s _ n w h b _ n , w l b _ n ( i a 1 8 6 e s ) , w b _ n ( i a 1 8 8 e s ) 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns c l k o u t a a 1 9 - a 0 s 6 / l o c k _ n a d 1 5 - a d 0 / a d 7 - a d 0 a o 1 5 - a o 8 a l e w r _ n w h b _ n / w l b _ n / w b _ n l c s _ n address address s6 lock_n s6 s6 address data data address address 65 68 8 7 30 9 23 11 34 10 33 32 31 5 20 20 31 87 80 81 80 84 ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 122 of 154 1 - 888 - 824 - 4184 table 82 . psram write cycle timing no. name description min a max a general timing requirements 1 tdvcl data in setup 10 C 2 tcldx data in hold 0 C general timing responses 5 tclav ad address valid delay 0 12 7 tcldv data valid delay 0 12 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 8 10 tlhll ale width tclch - 5 C 11 tchll ale inactive delay 0 8 20 tcvctv control active delay 1 0 10 23 tlhav ale high to address valid 7.5 C 80 tclclx lcs_n inactive delay 0 9 81 tclcsl lcs_n active d elay 0 9 84 tlrll lcs_n precharge pulse width tclcl+tclch C write cycle timing responses 30 tcldox data hold time 0 C 31 tcvctx control inactive delay 0 10 32 twlwh wr_n pulse width 2tclcl C 33 twhlh wr_n inactive to ale high tclch C 34 twhdx data h old after wr_n tclcl C 65 tavwl a address valid to wr_n low tclcl+tchcl C 68 tchav clkouta high to a address valid 0 8 87 tavbl a address valid to whb_n/wlb_n low tchcl - 1.5 tchcl a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 123 of 154 1 - 888 - 824 - 4184 figure 18 . psram refresh c ycle table 83 . psram refresh cycl e timing no. name description min a max a general timing requirements 1 tdvcl data in setup 10 C 2 tcldx data in hold 0 C general timing responses 9 tchlh ale active delay 0 8 10 tlhll ale wid th tclch - 5 C 11 tchll ale inactive delay 0 8 read/write cycle timing responses 25 tclrl rd_n active delay 0 10 26 trlrh rd_n pulse width tclcl C 27 tclrh rd_n inactive delay 0 10 28 trhlh rd_n inactive to ale high tclch C 80 tclclx lcs_n inactive de lay 0 9 81 tclcsl lcs_n active delay 0 9 refresh cycle timing responses 79 tchrfd clkouta high to rfsh_n valid 0 12 82 tclrf clkouta high to rfsh_n invalid 0 12 85 trfcy rfsh_n cycle time 6tclcl C 86 tlcrf lcs_n inactive to rfsh_n active delay 2tclcl C a in nanoseconds. ? c l k 0 a 1 9 C a 0 a l e r d _ n l c s _ n r f s h _ n 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns c l k 0 a 1 9 - a 0 a l e r d _ n l c s _ n r f s h _ n address address 9 11 10 26 28 27 27 80 81 25 79 82 86 85 ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 124 of 154 1 - 888 - 824 - 4184 figure 19 . interrupt acknowledge cycle ? c l k 0 a 1 9 C a 0 a l e b h e _ n ( i a 1 8 6 e s ) i n t a 1 _ n , i n t a 0 _ n a d 1 5 C a d 0 ( i a 1 8 6 e s ) , a d 7 C a d 0 ( i a 1 8 8 e s ) s 6 / l o c k _ n a o 1 5 C a o 8 ( i a 1 8 8 e s ) d e n _ n d t / r _ n s 1 _ n C s 0 _ n 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns clk0 a19 - a0 s6/lock_n ad15 - ad 0/ad7 - ad0 ao15 - ao8 ale bhe_n inta1_n/inta0_n den_n dt_r_n s2_n - s0_n address address s6 lock_n s6 s6 ptr address bhe_n bhe_n 68 7 8 12 1 2 9 23 15 10 11 4 31 20 22 19 22 22 21 3 4 ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 125 of 154 1 - 888 - 824 - 4184 table 84 . interrupt acknowledge cycle timing no. name description min a max a general timing requirements 1 tdvcl data in setup 10 C 2 tc ldx data in hold 0 C general timing responses 3 tchsv status active delay 0 6 4 tclsh status inactive delay 0 6 5 tclav ad address valid delay 0 12 9 tchlh ale active delay 0 8 10 tlhll ale width tclch - 5 C 11 tchll ale inactive delay 0 8 19 tdxdl d en_n inactive to dt/ r_n low 0 C 22 tchctv control active delay 2 0 10 68 tchav clkouta high to a address valid 0 8 a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 126 of 154 1 - 888 - 824 - 4184 figure 20 . software halt cycle ? c l k o u t a a 1 9 C a 0 a l e a d 1 5 C a d 0 ( i a 1 8 6 e s ) , a d 8 C a d 0 ( i a 1 8 8 e s ) , a o 1 5 C a o 8 ( i a 1 8 8 e s ) d e n _ n d t / r _ n s 1 _ n C s 0 _ n 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns c l k o u t a a 1 9 - a 0 s 6 / a d [ 1 5 : 0 / a d [ 8 : 0 ] / a o [ 1 5 : 8 ] a l e d e n _ n d t _ r _ n s 2 _ n - s 0 _ n invalid address invalid address invalid address invalid address status status 68 5 10 9 11 19 3 4 22 ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 127 of 154 1 - 888 - 824 - 4184 table 85 . software halt cycle timing no. name description min a max a general timing responses 3 tchsv status active delay 0 6 4 tclsh status inactive delay 0 6 7 tcldv data valid delay 0 12 8 tchdx status hold time 0 C 9 tchlh ale active delay 0 8 10 tlhll ale width tclch - 5 C 11 tchll ale inactive delay 0 8 12 tavll ad address valid to ale low tclch C 15 tclaz ad address float delay 0 12 16 tclcsv mcs_n/pcs_n inactive delay 0 12 17 tcxcsx mcs_n/pcs_n hold from command inactive tclch C 18 tchcsx mcs_n/pcs_n inactive delay 0 1 2 19 tdxdl den_n inactive to dt/ r_n low 0 C 20 tcvctv control active delay 1 0 10 21 tcvdex den_n inactive delay 0 9 22 tchctv control active delay 2 0 10 23 tlhav ale high to address valid 7.5 C 31 tcvctx control inactive delay 0 10 68 tchav clkout a high to a address valid 0 8 a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 128 of 154 1 - 888 - 824 - 4184 figure 21 . clock active mode figure 22 . clock power - save mode ? c l k o u t a x 2 x 1 c l k o u t b 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns x 2 x 1 c l k o u t a c l k o u t b 36 37 38 69 42 43 44 70 c l k o u t a x 2 x 1 c l k o u t b ( c b f = 1 ) c l k o u t b ( c b f = 0 ) 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns x 2 x 1 c l k o u t a c l k o u t b ( c b f = 1 ) c l k o u t b ( c b f = 0 ) ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 129 of 154 1 - 888 - 824 - 4184 table 86 . clock timing no. name description min a max a clki n requirements 36 tckin x1 period 25 66 37 tclck x1 low time 7.5 C 38 tchck x1 high time 7.5 C 39 tckhl x1 fall time C 5 40 tcklh x1 rise time C 5 clkout requirements 42 tclcl clkouta period 25 C 43 tclch clkouta low time tclcl/2 C 44 tchcl clkout a high time tclcl/2 C 45 tch1ch2 clkouta rise time 0 3 46 tcl2cl1 clkouta fall time 0 3 61 tlock maximum pll lock time C 0.5 69 tcicoa x1 to clkouta skew C 25 70 tcicob x1 to clkoutb skew C 35 a in nanoseconds. figure 23 . srdy synchronous ready ? c l k o u t a s r d y 0ns 20ns 40ns 60ns 80ns 100ns 120ns c l k o u t a s r d y 47 48 ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 130 of 154 1 - 888 - 824 - 4184 figure 24 . ardy asynchronous ready figure 25 . peripherals ? c l k o u t a a r d y a r d y a r d y 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns c l k o u t a a r d y a r d y a r d y sytem normally not ready sytem normally ready system normally ready 49 49 50 50 51 52 c l k o u t a i n t 4 C i n t 0 , n m i , t m r i n 1 C t m r i n 0 d r q 1 C d r q 0 t m r o u t 1 C t m r o u t 0 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns c l k o u t a i n t 4 - 0 / n m i / t m r i n 1 - 0 d r q 1 - d r q 0 t m r o u t 1 - t m r o u t 0 53 54 55 ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 131 of 154 1 - 888 - 824 - 4184 table 87 . ready and peripheral timing no. name description min a max a ready and peripher al timing requirements 47 tsrycl srdy transition setup time 10 C 48 tclsry srdy transition hold time 3 C 49 tarych ardy resolution transition setup time 9 C 50 tclarx ardy active hold time 4 C 51 tarychl ardy inactive holding time 6 C 52 tarylcl ardy setup time 9 C 53 tinvch peripheral setup time 10 C 54 tinvcl drq setup time 10 C peripheral timing responses 55 tcltmv timer output delay 0 12 a in nanoseconds. figure 26 . reset 1 figure 27 . r eset 2 ? x 1 r e s _ n c l k o u t a 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns x 1 r e s _ n c l k o u t a low for n x1 cycles 57 57 r f s h _ n / a d e n _ n , s 6 , u z i _ n r e s _ n c l k o u t a a d 1 5 C a d 0 ( i a 1 8 6 e s ) , a o 1 5 C a o 8 ( i a 1 8 8 e s ) , a d 7 C a d 0 ( i a 1 8 8 e s ) 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns r e s _ n c l k o u t a b h e _ n / a d e n _ n , r f s h 2 _ n / a d e n _ n / s 6 , u z i _ n a d [ 1 5 : 0 ] , a 0 [ 1 5 : 8 ] , a d [ 7 : 0 ] tri-state tri-state ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 132 of 154 1 - 888 - 824 - 4184 figure 28 . bus hold entering figure 29 . bus hold leaving ? a d 1 5 C a d 0 ( i a 1 8 6 e s ) , s 6 , r d _ n , w r _ n , b h e _ n ( i a 1 8 6 e s ) , d t / r _ n , s 2 _ n C s 1 _ n , w h b _ n , w l b _ n ( i a 1 8 6 e s ) h o l d c l k o u t a a d 1 5 C a d 0 ( i a 1 8 6 e s ) , d e n _ n h l d a 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns clkouta hold hlda ad[15:0],den_n s2_n-s1_n,whb_n,wlb_n 58 62 15 63 a d 1 5 C a d 0 ( i a 1 8 6 e s ) , s 6 , r d _ n , w r _ n , b h e _ n ( i a 1 8 6 e s ) , d t / r _ n , s 2 _ n C s 1 _ n , w h b _ n , w l b _ n ( i a 1 8 6 e s ) h o l d c l k o u t a a d 1 5 C a d 0 ( i a 1 8 6 e s ) , d e n _ n h l d a 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns clkouta hold hlda ad[15:0],den_n s2_n-s1_n,whb_n,wlb_n 58 62 5 64 ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 133 of 154 1 - 888 - 824 - 4184 table 88 . reset and bus hold timing no. name description min a max a reset and bus hold timing requirements 5 tclav ad address valid delay 0 12 15 tclaz ad address float delay 0 12 57 tresin res_n setup time 10 C 58 thvcl hld setup time 10 C reset and bus hold timing responses 62 tclhav hlda valid delay 0 7 63 tchcz command lines float delay 0 12 64 tchc v command lines valid delay (after float) 0 12 a in nanoseconds. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 134 of 154 1 - 888 - 824 - 4184 7. instruction set summary table table 89 summarizes each instruction. a key to abbreviations is presented at the end of the table. table 89 . instruction set summary instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 byte 3 C 6 ia186 es ia188 es o d i t s z a p c aaa ascii adjust al after add 37 C C 8 8 u C C C u u r u r aad ascii adjust ax before divide d5 0a C 15 15 u C C C r r u r u aam ascii adjust al after multiply d4 0a C 19 19 u C C C r r u r u aas ascii adjust al after subtract 3f C C 7 7 u C C C u u r u r adc add imm8 to al with carry 14 ib C 3 3 r C C C r r r r r add imm16 to ax with carry 15 iw C 4 4 add im m8 to r/m8 with carry 80 /2 ib C 4/16 4/16 add imm16 to r/m16 with carry 81 /2 iw C 4/16 4/20 add sign extended imm8 to r/m16 with carry 83 /2 ib C 4/16 4/20 add byte reg to r/m8 with carry 10 /r C 3/10 3/10 add word reg to r/m16 with carry 11 /r C 3/10 3/14 add r/m8 to byte reg with carry 12 /r C 3/10 3/10 add r/m16 to word reg with carry 13 /r C 3/10 3/14 add add imm8 to al 04 ib C 3 3 r C C C r r r r r add imm16 to ax 05 iw C 4 4 add imm8 to r/m8 80 /0 ib C 4/16 4/16 add imm16 to r/m16 81 /0 iw C 4/16 4/20 add sign extended imm8 to r/m16 83 /0 ib C 4/16 4/20 add byte reg to r/m8 00 /r C 3/10 3/10 add word reg to r/m16 01 /r C 3/10 3/14 add r/m8 to byte reg 02 /r C 3/10 3/10 add r/m16 to word reg 03 /r C 3/10 3/14 and and imm8 with al 24 ib C 3 3 0 C C C r r u r 0 and imm16 with ax 25 iw C 4 4 and imm8 with r/m8 80 /4 ib C 4/16 4/1 6 and imm16 with r/m16 81 /4 iw C 4/16 4/20 and sign - extended imm8 with r/m16 83 /4 ib C 4/16 4/20 and byte reg with r/m8 20 /r C 3/10 3/10 and word reg with r/m16 21 /r C 3/10 3/14 and r/m8 with byte reg 22 /r C 3/10 3/10 and r/m16 with word reg 23 /r C 3/10 3/14 bound check array index against bounds 62 /r C 33 C 35 33 C 35 C C C C C C C C C call call near, disp relative to next instruction e8 cw C 15 19 C C C C C C C C C call near , reg indirect mem ff /2 C 13/19 17/27 call far to full address given 9a cd C 23 31 call far to address at m16:16 word ff /3 C 38 54 cbw convert byte integer to word 98 C C 2 2 C C C C C C C C C clc clear carry flag f8 C C 2 2 C C C C C C C C C cld clear direction flag fc C C 2 2 C 0 C C C C C C C cli clear interrupt - enable flag fa C C 2 2 C C 0 C C C C C C cmc complement carry flag f5 C C 2 2 C C C C C C C C r refer to the key for abbreviations and an explanation of notation at the end of this table. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 135 of 154 1 - 888 - 824 - 4184 table 89. instruction set summary (continued) instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 byte 3 C 6 ia186 es ia188 es o d i t s z a p c cmp compare imm8 to al 3c ib C 3 3 r C C C r r r r r compare imm16 to ax 3d iw C 4 4 compare imm8 to r/m8 80 /7 ib 3/10 3/10 compare imm16 to r/m16 81 /7 iw 3/10 3/14 compare sign - extended imm8 to r/m16 83 /7 ib 3/10 3/14 compare byte reg to r/m8 38 /r C 3/10 3/10 compare word reg to r/m16 39 /r C 3/10 3/14 compare r/m8 to byte reg 3a /r C 3/10 3/10 compare r/m16 to word reg 3b /r C 3/10 3/14 cmps compare byte es : [di] to byte segment : [si] a6 C C 22 22 r C C C r r r r r compare word es : [di] to word segment : [si] a7 C C 22 26 cmpsb compare byte es : [di] to byte ds : [si] a6 C C 22 22 r C C C r r r r r cmpsw co mpare word es:[di] to word ds: [si] a7 C C 22 26 r C C C r r r r r cs cs segment reg override prefix 2e C C C C C C C C C C C C C cwd convert word integer to double word 99 C C 4 4 C C C C C C C C C daa decimal adjust al after a ddition 27 C C 4 4 ? C C C r r r r r das decimal adjust al after subtraction 2f C C 4 4 ? C C C r r r r r dec subtract 1 from r/m8 fe /1 C 3/15 3/15 r C C C r r r r r subtract 1 from r/m16 ff /1 C 3/15 3/19 subtract 1 from word reg 48+ rw 3 3 div divide unsigned numbers f6 mod 110 r/m C 29/35 29/35 u C C C u u u u u ds ds segment override prefix 3e C C C C C C C C C C C C C enter create stack frame for nested procedure c8 iw ib C 22+16 (n C 1) 26+20 (n C 1) C C C C C C C C C creat e stack frame for non - nested procedure c8 iw 00 C 15 19 create stack frame for nested procedure c8 iw 01 C 25 29 es es segment reg override prefix 26 C C C C C C C C C C C C C esc escape - takes a trap 7 d8 /0 C C C C C 0 0 C C C C C escape - takes a trap 7 d9 /1 C C C escape - takes a trap 7 da /2 C C C escape - takes a trap 7 db /3 C C C escape - takes a trap 7 dc /4 C C C escape - takes a trap 7 dd /5 C C C escape - takes a tr ap 7 de /6 C C C escape - takes a trap 7 df /7 C C C hlt suspend instruction execution f4 C C 2 2 C C C C C C C C C idiv divide integers al = ax/(r/m8); ah = remainder f6 /7 C 44 C 52 / 50 C 58 44 C 52 / 50 C 58 u C C C u u u u u divide int egers ax = dx : ax/(r/m16); dx = remainder f7 /7 C 53 C 61 / 59 C 67 53 C 61 / 63 C 71 refer to the key for abbreviations and an expl anation of notation at the end of this table. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 136 of 154 1 - 888 - 824 - 4184 table 89. instruction set summary (continued) instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 byte 3 C 6 ia186 es ia188 es o d i t s z a p c imul multiply integers ax=(r /m8)*al f6 /5 C 25 C 28 / 31 C 34 25 C 28 / 31 C 34 r C C C u u u u r multiply integers dx=(r/m16)*ax f7 /5 C 34 C 37 / 40 C 43 34 C 37 / 44 C 47 multiply integers (word reg) = (r/m16)*(sign - ext. byte integer) 6b /r ib C 22 C 25 22 C 25 multiply intege rs (word reg) = (word reg)*(sign - ext. byte integer) 6b /r ib C 22 C 25 22 C 25 multiply integers (word reg) = (r/m16)*(sign - ext. byte integer) 69 /r iw C 29 C 32 29 C 32 multiply integers (word reg) = (word reg)*(sign - ext. byte integer) 69 /r iw C 29 C 32 29 C 32 in input byte from imm port to al e4 ib C 10 10 C C C C C C C C C input word from imm port to ax e5 ib C 10 14 input byte from port in dx to al ec C C 8 8 input word from port in dx to ax ed C C 8 12 inc increment r/m8 by 1 fe /0 C 3/15 3/15 r C C C r r r r r increment r/m16 by 1 ff /0 C 3/15 3/19 increment word reg by 1 40+rw C C 3 3 ins input byte from port in dx to es : [di] 6c C C 14 14 C C C C C C C C C input word from port in dx to es : [di] 6d insb input byte from port in dx to es : [di] 6c insw input word from port in dx to es : [di] 6d int 3 generate interrupt 3 (trap to debug) cc C C 45 45 C C 0 0 C C C C C int generate type of interrupt specified by imm8 cd ib C 47 47 into generate interrupt 4 if overflow flag (o) is 1 ce C C 48, 4 48, 4 iret interrupt return cf C C 28 28 restores value of flags reg that was stored on the stack when the interrupt was taken j a jump short if above ( c & z = 0) 77 cb C 13, 4 13, 4 C C C C C C C C C jnbe jump short if not below or equal jae jump short if above or equal ( c =0) 73 cb C 13, 4 13, 4 C C C C C C C C C jnb jump short if not below ( c =0) jn c jump short if not carry ( c =0) jb jump short if below ( c =1) 72 cb C 13, 4 13, 4 C C C C C C C C C jc jump short if carry ( c =1) jnae jump short if not above or equal ( c =1) jbe jump short if below or equal ( c & z = 0) 76 cb C 13, 4 13, 4 C C C C C C C C C jna jump short if not above ( c & z = 0) refer to the key for abbreviations and an explanation of notation at the end of this table. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 137 of 154 1 - 888 - 824 - 4184 table 89. instruction set summary (continued) instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 byte 3 C 6 ia186 es ia188 es o d i t s z a p c jcxz jump sho rt if cx reg is 0 e3 cb C 15,5 15,5 C C C C C C C C C je jump short if equal ( z =1) 74 cb C 13, 4 13, 4 C C C C C C C C C jz jump short if 0 ( z =1) jg jump short if greater (z & s = o) 7f cb C 13, 4 13, 4 C C C C C C C C C jnle jump short if not less or equal ( z & s = o) jge jump short if greater or equal ( s =o) 7d cb C 13, 4 13, 4 C C C C C C C C C jnl jump short if not less (s = o) jle jump short if less or equal ( z & s = o) 7e cb C 13, 4 13, 4 C C C C C C C C C jng jump short if not greater (z & s = o) jmp jump short direct, disp relative to next instruction eb cb C 14 14 C C C C C C C C C jump near direct, disp relative to next instruction e9 cw C 14 14 jump near indirect ff /4 C 11/17 11/21 jump far direct to doubleword imm address ea cd C 14 14 jump m16: 16 indirect and far ff /5 C 26 34 jne jump short if not equal ( z =0) 75 cb C 13, 4 13, 4 C C C C C C C C C jnz jump short if not zero ( z =0) jno jump short if not overflow (o=1) 71 cb C 13, 4 13, 4 C C C C C C C C C jnp jump short if not parity ( p =0) 7b cb C 13, 4 13, 4 C C C C C C C C C jpo jump short if parity odd ( p =0) jns jump short if not sign ( s =0) 79 cb C 1 3, 4 13, 4 C C C C C C C C C jo jump short if overflow ( o =1) 70 cb C 13, 4 13, 4 C C C C C C C C C jp jump short if parity ( p =1) 7a cb C 13, 4 13, 4 C C C C C C C C C jpe jump short if parity ( p =1) js jump short if sign ( s =1) 78 cb C 13, 4 13, 4 C C C C C C C C C lahf load ah with low byte of flags reg 9f C C 2 2 C C C C C C C C C lds load ds:r16 with segment : offset from memory c5 /r C 18 26 C C C C C C C C C lea load offset for m16 word in 16 - bit reg 8d /r C 6 6 C C C C C C C C C leav e destroy procedure stack frame c9 C C 8 8 C C C C C C C C C les load es:r16 with segment offset from memory c4 /r C 18 26 C C C C C C C C C lock asserts lock_n during an instruction execution f0 C C 1 1 C C C C C C C C C lods load byte segment : [si] in al ac C C 12 12 C C C C C C C C C load word segment : [si] in ax ad 12 16 lodsb load byte ds : [si] in al ac 12 12 lodsw load word ds : [si] in ax ad 12 16 loop decrement count; jump short if cx 0 e2 C C 16, 6 16, 6 C C C C C C C C C loope decrement count; jump short if cx 0 and z = 1 e1 cb C loopz decrement count; jump short if cx 0 and z = 1 loopne decrement count; jump short if cx 0 and z = 0 e0 cb C 16, 6 16, 6 C C C C C C C C C loopnz decrement count; jump short if cx 0 and z = 0 refer to the key for abbreviations and an explanation of notation at the end of this table. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 138 of 154 1 - 888 - 824 - 4184 table 89. instruction set summary (continued) instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 byte 3 C 6 ia186 es ia188 es o d i t s z a p c mov copy reg to r/m8 88 /r C 2/12 2/12 C C C C C C C C C copy reg to r/m16 89 /r C 2/12 2/16 copy r/m8 to reg 8a /r C 2/9 2/9 copy r/m16 to reg 8b /r C 2/9 2/13 copy segment reg to r/m16 8c /sr C 2/11 2/15 copy r/m16 to segment reg 8e /sr C 2/9 2/13 copy byte at segment offset to al a0 C C 8 8 copy word at segment offset to ax a1 C C 8 12 copy al to byte at segment offset a2 C C 9 9 copy ax to word at segment offset a3 C C 9 13 copy imm8 to reg b0+rb C C 3 3 copy imm16 to reg b8+rw C C 3 4 copy imm8 to r/m8 c6 /0 C 12 12 copy imm16 to r/m16 c7 /0 C 12 13 movs copy byte segment [si] to es:[di] a4 C C 14 14 C C C C C C C C C copy word segment [si] to es:[di] a5 C C 14 18 movsb copy byte ds:[si] to es:[di] a4 C C 14 14 movsw copy word ds:[si] to es:[di] a5 C C 14 18 mul ax = (r/m8) * al f6 /4 C 26 C 28 / 32 C 34 26 C 28 / 32 C 34 r C C C C C C C r dx :: ax = (r/m16) * ax f7 /4 35 C 37 / 41 C 43 35 C 37 / 45 C 47 neg perform 2's - complement negation of r/m8 f6 /3 C 3/10 3/10 r C C C r r r r r perform 2's - complement negation of r/m16 f7 /3 C 3/10 3/14 nop perform no operation 90 C C 3 3 C C C C C C C C C not complement each bit in r/ m8 f6 /2 C 3/10 3/10 C C C C C C C C C complement each bit in r/m16 f7 /2 3/10 3/14 or or imm8 with al 0c ib C 3 3 0 C C C r r u r 0 or imm16 with ax 0d iw C 4 4 or imm8 with r/m8 80 /1 ib C 4/16 4/16 or imm16 with r/m1 6 81 /1 iw C 4/16 4/20 or imm8 with r/m16 83 /1 ib C 4/16 4/20 or byte reg with r/m8 08 /r C 3/10 3/10 or word reg with r/m16 09 /r C 3/10 3/14 or r/m8 with byte reg 0a /r C 3/10 3/10 or r/m16 with wor d reg 0b /r C 3/10 3/14 out output al to imm port e6 ib C 9 9 C C C C C C C C C output ax to imm port e7 ib C 9 13 output al to port in dx ee C C 7 7 output ax to port in dx ef C C 7 11 outs output byte ds:[si] t o port in dx 6e C C 14 14 C C C C C C C C C output word ds:[si] to port in dx 6f C C outsb output byte ds:[si] to port in dx 6e C C outsw output word ds:[si] to port in dx 6f C C refer to the key for abbreviations and an explanation of notation at the end of this table. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 139 of 154 1 - 888 - 824 - 4184 table 89. instruction set summary (continued) instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 byte 3 C 6 ia186 es ia188 es o d i t s z a p c pop pop top word of stack into memory word 8f /0 C 20 24 C C C C C C C C C pop top word of stack into word reg 58+rw C C 10 14 pop top word o f stack into ds 1f C C 8 12 pop top word of stack into es 07 C C pop top word of stack into ss 17 C C popa pop di, si, bp, bx, dx, cx, & ax 61 C C 51 83 values in word at top of stack are copied into flags reg bits popf pop top word of stack into processor status flags reg 9d C C 8 12 push push memory word onto stack ff /6 C 16 20 C C C C C C C C C push reg word onto stack 50+rw C C 10 14 push sign - extended imm8 onto stack 6a C C 10 14 push imm1 6 onto stack 68 C C 10 14 push cs onto stack 0e C C 9 13 push ss onto stack 16 C C 9 13 push ds onto stack 1e C C 9 13 push es onto stack 06 C C 9 13 pusha push ax, cx, dx, bx, original sp, bp, si, and di 60 C C 36 68 C C C C C C C C C pushf push processor status flags reg 9c C C 9 13 C C C C C C C C C rcl rotate 9 bits of c and r/m8 left once d0 /2 C 2/15 2/15 C C C C C C C C C rotate 9 bits of c and r/m8 left cl times d2 /2 C 5+n/ 17+n 5+n/ 17+n rotate 9 bits of c and r/m8 left imm8 times c0 /2 ib C 5+n/ 17+n 5+n/ 17+n rotate 17 bits of c and r/m16 left once d1 /2 C 2/15 2/15 rotate 17 bits of c and r/m16 left cl times d3 /2 C 5+n/ 17+n 5+n/ 17+n rotate 17 bits of c and r/m16 left imm8 times c1 /2 ib C 5+n/ 17+n 5+n/ 17+n rcr rotate 9 bits of c and r/m8 right once d0 /3 C 2/15 2/15 C C C C C C C C C rotate 9 bits of c and r/m8 right cl times d2 /3 C 5+n/ 17+n 5+n/ 17+n rotate 9 bi ts of c and r/m8 right imm8 times c0 /3 ib C 5+n/ 17+n 5+n/ 17+n rotate 17 bits of c and r/m16 right once d1 /3 C 2/15 2/15 rotate 17 bits of c and r/m16 right cl times d3 /3 C 5+n/ 17+n 5+n/ 17+n rotate 17 bits of c and r/ m16 right imm8 times 75 /3 ib C 5+n/ 17+n 5+n/ 17+n rep ins input cx bytes from port in dx to es : [di] f3 6c C 8+8n 8+8n C C C C C C C C C input cx bytes from port in dx to es : [di] f3 6d C 8+8n 12+8n rep lods load cx bytes from segment : [si] in al f3 ac C 6+11n 6+11n C C C C C C C C C load cx words from segment : [si] in ax f3 ad C 6+11n 10+ 11n refer to the key for abbreviations and an explanation of notation at the end of this table. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 140 of 154 1 - 888 - 824 - 4184 table 89. instruction set summary (continued) instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 byte 3 C 6 ia186 es ia188 es o d i t s z a p c rep movs copy cx bytes from segments : [si] to es:[di] f3 a4 C 8+8n 8+8n C C C C C C C C C copy cx words from segments : [si] to es:[di] f3 a5 C 8+8n 12+8n rep outs output cx bytes from ds:[si] to port in dx f3 6e C 8+8n 8+8n C C C C C C C C C output cx bytes from ds:[si] to port in dx f3 6f C 8+8n 12+8n rep stos fill cx bytes at es:[di] with al f3 aa C 8+8n 8+8n C C C C C C C C C fill cx words at es:[di] with al f3 ab C 8+8n 12+8n repe cmps find non - matching bytes i n es:[di] and segment : [si] f3 a6 C 5+22n 5+22n C C C C C C C C C find non - matching words in es:[di] and segment : [si] f3 a7 C 5+22n 9+22n repe scas find non - al byte starting at es:[di] f3 ae C 5+15n 5+15n find non - ax word starting at es:[di] f3 af C 5+15n 9+15n repz cmps find non - matching bytes in es:di and segment : [si] f3 a6 C 5+22n 5+22n find non - matching words in es:di and segment : [si] f3 a7 C 5+22n 9+22n repz scas find non - al byte starting at es:di f3 ae C 5+15n 5+15n find non - ax word starting at es:di f3 af C 5+15n 9+15n repne cmps find matching bytes in es:[di] and segment : [si] f2 a6 C 5+22n 5+22n C C C C C C C C C find matching words in es:[di] and segment : [si] f2 a7 C 5+22n 9 +22n repnz cmps find al byte starting at es:[di] f2 a6 C 5+22n 5+22n find ax word starting at es:[di] f2 a7 C 5+22n 9+22n repne scas find matching bytes in es:di and segment : [si] f2 ae C 5+15n 5+15n find matching w ords in es:di and segment : [si] f2 af C 5+15n 9+15n repnz scas find al byte starting at es:di f2 ae C 5+15n 5+15n find ax word starting at es:di f2 af C 5+15n 9+15n ret return near to calling procedure c3 C C 16 20 C C C C C C C C C return far to calling procedure cb data low data high 22 30 return near; pop imm16 parameters c2 C C 18 22 return far; pop imm16 parameters ca data low data high 25 33 rol rotate 8 bits of r/m8 left once d0 /0 C 2/1 5 2/15 u C C C C C C C r rotate 8 bits or r/m8 left cl times d2 /0 C 5+n/ 17+n 5+n/ 17+n rotate 8 bits or r/m8 left imm8 times c0 /0 ib data 8 5+n/ 17+n 5+n/ 17+n rotate 16 bits of r/m8 left once d1 /0 C 2/15 2/15 rol rota te 16 bits or r/m8 left cl times d3 /0 C 5+n/ 17+n 5+n/ 17+n u C C C C C C C r rotate 16 bits or r/m8 left imm8 times c1 /0 ib data 8 5+n/ 17+n 5+n/ 17+n refer to the key for abbrevia tions and an explanation of notation at the end of this table. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 141 of 154 1 - 888 - 824 - 4184 table 89. instruction set summary (continued) instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 byte 3 C 6 ia186 es ia188 es o d i t s z a p c ror rotate 8 bits of r/m8 right once d0 /1 C 2/15 2/15 u C C C C C C C r rotate 8 bits or r/m8 right cl times d2 /1 C 5+n/ 17+n 5+n/ 17+n rotate 8 bits or r/m8 right imm8 times c0 /1 ib data 8 5+n/ 17+n 5+n/ 17+n rotate 16 bits of r/m8 right once d1 /1 C 2/15 2/15 rotate 16 bits or r/m8 right cl times d3 /1 C 5+n/ 17+n 5+n/ 17+n rotate 16 bits or r/m8 right imm8 times c1 /1 ib data 8 5+n/ 17+n 5+n/ 17+n sahf show ah in low byte of the status flags reg 9e C C 3 3 C C C C r r r r r sal/shl multiply r/m8 by 2, once d0 /4 C 2/15 2/15 u C C C C r r r r multiply r/m8 by 2, cl times d2 /4 C 5+n/ 17+n 5+n/ 17+n multiply r/m8 by 2, imm8 times c0 /4 ib data 8 5+n/ 17+n 5+n/ 17+n multiply r/m16 by 2, once d1 /4 C 2/15 2/15 multiply r/m16 by 2, cl times d3 /4 C 5+n/ 17+n 5+n/ 17+n multiply r/m16 by 2, imm8 times c1 /4 ib data 8 5+n/ 17+n 5+n/ 17+n multiply r/ m8 by 2, once d0 /4 C 2/15 2/15 multiply r/m8 by 2, cl times d2 /4 C 5+n/ 17+n 5+n/ 17+n multiply r/m8 by 2, imm8 times c0 /4 ib data 8 5+n/ 17+n 5+n/ 17+n multiply r/m16 by 2, once d1 /4 C 2/15 2/15 multiply r/m 16 by 2, cl times d3 /4 C 5+n/ 17+n 5+n/ 17+n multiply r/m16 by 2, imm8 times c1 /4 ib data 8 5+n/ 17+n 5+n/ 17+n sar perform a signed division of r/m8 by 2, once d0 /7 C 2/15 2/15 u C C C r r u r r perform a signed division of r/m8 b y 2, cl times d2 /7 C 5+n/ 17+n 5+n/ 17+n perform a signed division of r/m8 by 2, imm8 times c0 /7 ib data 8 5+n/ 17+n 5+n/ 17+n perform a signed division of r/m16 by 2, once d1 /7 C 2/15 2/15 perform a signed division of r /m16 by 2, cl times d3 /7 C 5+n/ 17+n 5+n/ 17+n perform a signed division of r/m16 by 2, imm8 times c1 /7 ib data 8 5+n/ 17+n 5+n/ 17+n refer to the key for abbreviations an d an explanation of notation at the end of this table. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 142 of 154 1 - 888 - 824 - 4184 table 89. instruction set summary (continued) instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 by te 3 C 6 ia186 es ia188 es o d i t s z a p c sbb subtract imm8 from al with borrow 1c ib C 3 3 r C C C r r r r r subtract imm16 from ax with borrow 1d iw data 8 4 4 subtract imm8 from r/m8 with borrow 80 /3 ib C 4/16 4/16 subtract imm1 6 from r/m16 with borrow 81 /3 iw C 4/16 4/20 subtract sign - extended imm8 from r/m16 with borrow 83 /3 ib C 4/16 4/20 subtract byte reg from r/m8 with borrow 18 /r data 8 3/10 3/10 subtract word reg from r/m16 with borrow 19 /r C 3/10 3/14 subtract r/m8 from r/m8 with borrow 1a /r C 3/10 3/10 subtract r/m8 reg from byte with borrow 1b /r data 8 3/10 3/14 scas compare byte al to es:[di]; update di ae C C 15 19 r C C C r r r r r compare word al to es:[di]; update di af C C 15 19 scasb compare byte al to es:[di]; update di ae C C 15 19 scasw compare word al to es:[di]; update di af C C 15 19 shr divide unsigned of r/m8 by 2, once d0 /7 C 2/15 2/15 u C C C r r u r 0 divide unsigned of r/m8 by 2, cl times d2 /7 C 5+n/ 17+n 5+n/ 17+n divide unsigned of r/m8 by 2, imm8 times c0 /7 ib data 8 5+n/ 17+n 5+n/ 17+n divide unsigned of r/m16 by 2, once d1 /7 C 2/15 2/15 divide unsigned of r/m16 by 2, cl times d3 /7 C 5+n/ 17+n 5+n/ 17+n divide unsigned of r/m16 by 2, imm8 times c1 /7 ib data 8 5+n/ 17+n 5+n/ 17+n ss ss segment reg override prefix 36 C C C C C C C C C C C C C stc set the carry flag to 1 f9 C C 2 2 C C C C C C C C 1 std set the direction flag so the source index (si) and/or the destination index (di) regs will decrement during string instructions fd C C 2 2 C 1 C C C C C C C sti enable maskable interrupts after the next instruction fb C C 2 2 C C 1 C C C C C C stos store al in byte es:[di]; update di aa C C 10 10 C C C C C C C C C store ax in word es:[di]; update di ab C C 10 14 stosb store al in byte es:[di]; update di aa C C 10 10 stosw store ax in word es:[di]; update di ab C C 10 14 refer to the key for abbreviations and an explanation of notation at the end of this table. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 143 of 154 1 - 888 - 824 - 4184 table 89. instruction set s ummary (continued) instruction opcode C hex clock cycles flags affected mnemonic description b yte 1 byte 2 byte 3 C 6 ia186 es ia188 es o d i t s z a p c sub subtract imm8 from al 2c ib C 3 3 r C C C r r r r r subtract imm16 from ax 2d iw C 4 4 subtract imm8 from r/m8 80 /5 ib C 4/16 4/16 subtract imm16 from r/m16 81 /5 iw C 4/16 4/20 subtract sign - extended imm8 from r/m16 83 /5 ib C 4/16 4/20 subtract byte reg from r/m8 28 /r C 3/10 3/10 subtract word reg from r/m16 29 /r C 3/10 3/14 subtract r/m8 from byte reg 2a /r C 3/10 3/10 subtract r/m16 from word reg 2b /r C 3/10 3/14 test and imm8 with al a8 ib C 3 3 0 C C C r r u r 0 and imm16 with ax a9 iw C 4 4 and imm8 with r/m8 f6 /0 ib data 8 4/10 4/10 and imm16 with r/m16 f7 /0 iw C 4/10 4/14 and byte reg with r/m8 84 /r C 3/10 3/10 and word reg with r/m16 85 /r data 8 3/10 3/14 wait performs a nop 9b C C C C C C C C C C C C C xchg exchange word reg with ax 90 +rw C C 3 3 C C C C C C C C C exchange ax with word reg C C 3 3 exchange byte reg with r/byte 86 /r C C 4/17 4/17 exchange r/m8 with byte reg C C 4/17 4/17 exchange word reg wi th r/m16 87 /r C C 4/17 4/21 exchange r/m16 with word reg C C 4/17 4/21 xlat set al to memory byte segment : [bx+unsigned al] d7 C C 11 15 C C C C C C C C C xlatb set al to memory byte ds : [bx+unsigned al] d7 C C 11 15 xor xor imm8 with al 34 ib C 3 3 0 C C C r r u r 0 xor imm16 with ax 35 iw C 4 4 xor imm8 with r/m8 80 /6 ib C 4/16 4/16 xor imm16 with r/m16 81 /6 iw C 4/16 4/20 xor sign - extended imm8 with r/m16 83 /6 ib C 4/16 4/20 xor byte reg with r/m8 30 /r C 3/10 3/10 xor word reg with r/m16 31 /r C 3/10 3/14 xor r/m8 with byte reg 32 /r C 3/10 3/10 xor r/m16 with word reg 33 /r C 3/10 3/14 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 144 of 154 1 - 888 - 824 - 4184 7.1 key to abbreviations used in instruction set summary table abbreviations used in the instruction set summary table are explained below. 7.1.1 operand address byte the operand address byte is configured as shown below . 7 6 5 4 3 2 1 0 mod field aux field r/ m field 7.1.2 modifier field the modifier field is defined below. mod description 11 r/m is treated as a register field 00 disp = 0, dis p - low and disp - high are absent, address displacement is 0 01 disp = disp - low sign - extended to 16 - bits, disp - high is absen t 10 disp = disp - high: disp - low 7.1.3 auxiliary field the auxiliary field is defined below. aux if mod = 11 and word = 0 if mod = 11 and word = 1 000 al ax 001 cl cx 010 dl dx 011 bl bx 100 ah sp 101 ch bp 110 dh si 111 bh di note: when mod 11, dep ends on instruction . ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 145 of 154 1 - 888 - 824 - 4184 7.1.4 r/m field the r/m field is defined below. r/m description 000 ea = (bx) + (si) + disp [where ea is the effective address] 001 ea = (bx) + (di) + disp 010 ea = (bp) + (si) + disp 011 ea = (bx) + (di) + disp 100 ea = (si) + disp 1 01 ea = (di) + disp 110 ea = (bp) + disp [except if mod = 00, then ea = disp - high:disp - low] 111 ea = (bx) + disp 7.1.5 displacement the displacement is an 8 - or 16 - bit value added to the offset portion of the address. 7.1.6 immediate bytes the immediate bytes cons ist of up to 16 bits of immediate data. 7.1.7 segment override prefix the segment override prefix is configured as shown below . 7 6 5 4 3 2 1 0 0 0 1 sr sr 1 1 0 7.1.8 segment register the segment register is shown below. sr segment register 00 es 01 cs 10 ss 11 ds ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 146 of 154 1 - 888 - 824 - 4184 7.2 explanation of notation used in instruction set summary table notation used in the instruction set summary table is explained below. parameter indication : the component of the left is the segment for a component located in memory. the component on the right is the offset. :: the component of the left is concatenated with the component on the right. operand definition imm8 immediate byte: signed number between C 128 and 127 imm16 immediate wor d: signed number between C 32768 and 32767 m operand in memory m8 byte string in memory pointed to by ds:si or es:di m16 word string in memory pointed to by ds:si or es:di r/m8 general byte register or a byte in memory r/m16 general word register or a word in memory 7.2.1 opcode opcode parameters and definitions are provided below. parameter definition /0 - /7 the auxiliary field in the operand address byte specifies an extension (from 000 to 111, i.e., 0 to 7) to the opcode instead of a register. thus, t he opcode for adding (and) an immediate byte to a general byte register or a byte in memory is 80 /4 ib . this indicates that the second byte of the opcode is mod 100 r/m. /r the auxiliary field in the operand address byte specifies a register rather that an opcode extension. the opcode byte specifies which register, either byte size or word size, is assigned as in the aux code above. /sr this byte is placed before the instruction as shown in section 7.1.7, s egment override prefix . cb the byte following the opcode byte specifies the offset. cd the double word following the opcode byte specifies the offset and is some cases a segment. ib immediate byte signed or unsigned determined by the opcode byte. iw i mmediate word signed or unsigned determined by the opcode byte. rw word register operand as determined by the opcode byte, aux field. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 147 of 154 1 - 888 - 824 - 4184 7.2.2 flags affected after instruction flags affected after instruction are shown below. u undefined - unchanged r result dependent ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 148 of 154 1 - 888 - 824 - 4184 8. innovasic /amd part number cross - reference tables tables 90 and 9 1 show innovasic part numbers cross - reference d with the corresponding amd part number . table 90 . innovasic /amd part number cross - reference for the tqfp innovasic part number amd part number package type temperature grades ia186es - ptq100i - r - 03 lead free ( rohs - compliant ) am186es - 20vc \ w am186es - 25vc \ w am186es - 33vc \ w am186es - 40vc \ w am186es - 20 vi \ w am186es - 25 vi \ w am186es - 33 vi \ w am186es - 40 vi \ w 100 - pin thin qua d flat package (tqfp) industrial ia188es - ptq100i - r - 03 lead free ( rohs - compliant ) am188es - 20vc \ w am188es - 25vc \ w am188es - 33vc \ w am188es - 40vc \ w am188es - 20 vi \ w am188es - 25 vi \ w am188es - 33 vi \ w am188es - 40 vi \ w ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 149 of 154 1 - 888 - 824 - 4184 table 91 . innovasic /am d part number cross - reference for the pqfp innovasic part number amd part number package type temperature grade ia186es - pqf100i - r - 03 lead free ( rohs - compliant ) am186es - 20kc \ w am186es - 25kc \ w am186es - 33kc \ w am186es - 40kc \ w am186es - 20 ki \ w am186es - 25 ki \ w am186 es - 33 ki \ w am186es - 40 ki \ w 100 - pin plastic quad flat package (pqfp) industrial ia188es - pqf100i - r - 03 lead free ( rohs - compliant ) am188es - 20kc \ w am188es - 25kc \ w am188es - 33kc \ w am188es - 40kc \ w am188es - 20 ki \ w am188es - 25 ki \ w am188es - 33 ki \ w am188es - 40 ki \ w ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 150 of 154 1 - 888 - 824 - 4184 9. er rata the following errata are associated with version 03 of the ia186es/ia188es. a workaround to the identified problem has been provided where possible. 9.1 errata summary table 9 2 presents a summary of errata. table 92 . summary of e rrata errata no. problem ver. 0 3 1 there is a difference in how priority of timer interrupts are asserted between the original amd part and the innovasic part. exists 2 lock up just after reset is released. exists 3 intermittent startup. exists 4 timer operation in continuous mode. exists 5 dma interrupt will not bring device out of halt state. exists 6 does not clear the interrupt req bit for int0 upon entering the isr. exists 7 there is a difference in how hardware handshaking for uarts during a bu s hold cycle is handled between the original amd part and the innovasic part. exists 9.2 errata detail errata no. 1 problem: there is a difference in how priority of timer interrupts are asserted between the original amd part and th e innovasic part. description: in the original amd part, timer interrupts cannot be interrupted by another timer interrupt, even if the new timer interrupt is of a higher priority. the innovasic part will interrupt a timer interrupt with a higher - priorit y timer interrupt. additionally, if a lower - priority timer interru pt is interrupted with a higher - priority timer interrupt and another incident of the lower - priority interrupt occurs duri ng the processing of the higher - priority interrupt, upon execution o f the eoi , a new lower - priority interrupt will be initiated, possib ly orphaning the original lower - priority timer interrupt. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 151 of 154 1 - 888 - 824 - 4184 workaround: when using nested interrupts, at the beginning of the interrupt routine before the global interrupts are enabled with a cli, timer interrupts must be specifically masked. at the end of the timer interrupt routine being serviced, set the interrupt enable bit in the process status word to globally disable interrupts prior to clearing the timer interrupt being serviced and unmask the appropriate timer interrupts. errata no. 2 problem: lock up just after reset is released. description: usually the first instruction is a lon g jump to the start of the user s code. in this case, the compiler apparentl y inserted a short jump instruction with zero displacement before the expected long jump instruction. the oem device stuttered, but recovered to execute the long jump, while the device instruction pointer was corrupted, causing the lock up. in summary, a short jump with zero displacement is a corner c ase that does not work in the device. workaround: do not use a short jump instruction with zero displacement. errata no. 3 problem: intermittent startup. description: processor eith er came out of reset normally, or would go into a series of watchdog timeouts. the addition of 10k ohm pullups to the wr _n and rd _n outputs seemed to solve the issue. further analysis of the oem device shows the presence of undocumented pullups on these pins, which will pull them high when the reset condition tristates these pins. the device does not include internal pullups on these pins allowing these outputs to float during reset. workaround: add 10k ohm pullups to wr _n and rd _n pins to guarantee pro per logic levels at the end of reset. errata no. 4 problem: timer operation in continuous mode. description: the timers (timer0 and timer1) do not function per the specification when set in continuous mode with no external timer input stimulus to initiate/continue count. workaround: none. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 15 2 of 154 1 - 888 - 824 - 4184 errata no. 5 problem: dma interrupt will not bring device out of halt state . description: when device is in halt state, the interrupt caused by a dma completion will n ot bring the cpu out of the halt state. workaround: use idle mode instead of halt. errata no. 6 problem: does not clear the interrupt req bit for int0 upon entering the isr. description: the interrupt bit for int0 is not cleared until the interrupt routine is complete. workaround: do not rely on the bit to be cleared when nesting interrupts. errata no. 7 problem: how hardware handshaking for uarts during a bus hold cycle is handled differently between t he amd part and the innovasic part. description: in the amd part, hardware handshaking works per the data sheet. the innovasic part will occasionally drive a handshake signal to the incorrect state during bus hold instead of tri stating the pin. workaroun d: none. avoid using hardware handshaking in conjunction with the bus hold op eration with the innovasic part uarts. ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 153 of 154 1 - 888 - 824 - 4184 10. revision history table 9 3 presents the sequence of revisions to document ia 2110 50902. table 93 . revision histo ry date revision description page(s) august 17, 2007 11 e dition released . na january 31, 2008 12 errata 6 and 7 added. 136 february 19, 2008 13 errata 7 clarified . 136 august 7, 2008 14 column 2 of periphe ral control regis ters table changed from serial port 0 to serial port 1 in 6 bottom rows. 9 december 24, 2008 15 document reformatted and elements added to meet publication standards . improved f igures and tables . added conventions , acronyms and abbreviations , and summary of errata table . all january 25, 2010 16 corrected pqfp package dimensions table . 30 february 25, 2011 17 updated section 2.2.50 to clarify that power rating is + 10%; removed packaging options to support the elimination of snpb lead plating options. 44, 148, 149 july 22, 2011 18 corrected pin names for various pins. 17 - 29 november 15, 2011 19 corrected pin names for pins 42, 43 29 ? ia 186es/ia188es data sheet 8 - bit/16 - bit microcontrollers november 15 , 2011 ia211050902 - 1 9 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 154 of 154 1 - 888 - 824 - 4184 11. for additional information the ia186es/ ia 188es is a form, fit, and function replacement for the original amd am186es/188es family of microcontrollers. innovasic produces replacement ics using its miles system cloning technology that p roduces replacement ics far more complex than emulation while ensuring they are compatible with the original ic. miles captures the design of a clone so it can be produced even as silicon technology advances. miles also verifies the clone against the o riginal ic so that even the undocumented features are duplicated. the ia186es/ia188es family of microcontrollers replaces obsolete amd am186es/188es devices, allowing customers to retain existing board designs, software compilers/assemblers, and emulat ion tools and thus avoid expensive redesign efforts. the innovasic support team wants its information to be complete, accurate, useful, and easy to understand. please feel free to contact experts at innovasic with suggestions, comments, or questions at an y time . innovasic support team 3737 princeton ne suite 130 albuquerque, nm 87107 phone: +1 505 - 883 - 5263 fax: +1 505 - 883 - 5477 toll free: (888) 824 - 4184 website: http://www.innovasic.com ? |
Price & Availability of IA186ES-PTQ100I-R-03
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |